Hybrid and heterogeneous photonic integration

Increasing demand for every faster information throughput is driving the emergence of integrated photonic technology. The traditional silicon platform used for integrated electronics cannot provide all of the functionality required for fully integrated photonic circuits, and thus, the last decade has seen a strong increase in research and development of hybrid and heterogeneous photonic integrated circuits. These approaches have enabled record breaking experimental demonstrations, harnessing the most favorable properties of multiple material platforms, while the robustness and reliability of these technologies are suggesting entirely new approaches for precise mass manufacture of integrated circuits with unprecedented variety and flexibility. This Tutorial provides an overview of the motivation behind the integration of different photonic and material platforms. It reviews common hybrid and heterogeneous integration methods and discusses the advantages and shortcomings. This Tutorial also provides an overview of common photonic elements that are integrated in photonic circuits. Finally, an outlook is provided about the future directions of the hybrid/heterogeneous photonic integrated circuits and their applications.


I. INTRODUCTION
Integrated circuit technology has underpinned the information revolution, enabling our computers, our smart phones, and the information superhighway that connects us. From the very early stages of this technology, there has been a push to have more and more functionalities monolithically integrated with ever more complex circuits using the same material and technology platform. However, traditional technology platforms have matured and reached a plateau primarily limited by the bandwidth constraints imposed by electronic input/output interfaces. The need to overcome this electronic bottleneck has led to the advent of integrated photonics with the aim of providing a direct interface to the vast bandwidth that is currently available with fiber optics.
Optical fiber systems are typically composed of discrete elements, such as lasers, modulators, and detectors often packaged in a rack scale module. Photonic integrated circuits (PICs) are particularly attractive as they can shrink down these rack scale photonic modules to a chip the size of a thumb nail-similar to the integrated electronics that they interface. The integration of such systems on a chip comes with additional benefits, such as energy efficiency, robustness, weight reduction, and ultra-fast feedback control. In the laboratory, these properties have enabled unprecedented scientific demonstrations, such as chip-scale optical frequency synthesizers, 1 battery operated optical frequency comb sources, 2 and high-speed optical communication experiments. 3 Industrially, companies, such as Cisco, Juniper, Infinera Corporation, and Huawei, 4 are already offering commercial products using PICs for broadband interfacing of electronics; however, many are exploring the potential of PICs for more sophisticated information processing functionalities as well.
PICs with many different waveguide material technologies have been investigated over the years, such as silicon (Si), 5,6 silicon nitride (Si 3 N 4 ), [7][8][9] doped silicon dioxide (SiO 2 ), 10 gallium arsenide (GaAs), 11,12 indium phosphide (InP), [13][14][15] lithium niobate (LiNbO 3 ), 16 aluminum nitride (AlN), [17][18][19] and gallium nitride (GaN). [17][18][19] Arguably, the most prominent waveguide material technology is silicon. The benefit of silicon is the availability of high-quality wafer scale silicon thin-films, which can be patterned with mature fabrication processes, due to the fabrication advances of the complementary metal-oxide-semiconductor (CMOS) APL Photonics TUTORIAL scitation.org/journal/app technology driven by the demand of consumer electronics and the potential to monolithically integrate silicon electronics and photonics on the same platform. 20 However, over the years, it also became clear that silicon cannot fulfill the needs for all applications that would benefit from PICs. For example, it is difficult to achieve light sources in silicon due to its indirect bandgap. Silicon also suffers from two photon absorption (TPA) at typical communication wavelengths, which makes it difficult to be used for nonlinear optical applications. 21,22 Other waveguide materials may overcome some of the shortcomings of silicon, but they may have other limitations for the target applications. Current trends in PIC material technologies indicate that there is no waveguide material technology that can address the needs for all the potential applications of PICs. Furthermore, advanced PICs may require the best possible performance of a large number of different photonic elements in a PIC to achieve the desired functionality, which may not be possible with a single waveguide material technology. A solution to overcome this limitation is to integrate different material technologies into a single PIC or package. This approach has the benefit that each material can be used to provide the photonic element functionality for which it is best suited without compromising the functionalities of the other elements in the system. The integration of the different material technologies can be distinguished by two different integration processes: (i) hybrid integration and (ii) heterogeneous integration.
In this Tutorial, we provide an overview of the hybrid and heterogeneous photonic integration. In Sec. II, we examine different material technologies that are relevant for hybrid/heterogeneous integration. Section III gives a brief introduction into hybrid and heterogeneous integration, and Sec. IV describes diverse ways different material technologies can be interfaced with each other to allow for low loss transitions among them. In Sec. V, we analyze the different integration methods that can be used for the hybrid/heterogeneous integration of photonic circuit elements. Section VI gives an overview of hybrid and heterogeneous integration examples for real world applications, and Sec. VII takes a look into future trends before concluding in Sec. VIII.

II. MATERIAL TECHNOLOGIES
Many different material technologies have been investigated in the decades of research on PICs, motivated by the aim of utilizing the best available material properties for a specific application. Some of the most important material properties for PICs are the refractive index, transparency across various wavelength ranges, the direct/indirect semiconductor bandgap, nonlinear optical properties [χ (2) and χ (3) ], the electro-optic coefficient, the piezoelectric coefficient, the thermo-optic coefficient, acousto-optic properties, and low waveguide propagation losses. It should be noted that this is not a complete list of materials and platform properties that are attractive for PICs but are some of the most important ones and will be further examined in the following.
The refractive index is an important material property for most optical waveguide platforms as it defines the achievable refractive index contrast between waveguide core and surrounding materials. A higher refractive index contrast is beneficial to achieve a tight waveguide bending radius and, therefore, a high integration density as well as the ability to confine the optical waveguide mode tightly.
The width of the waveguide material bandgap is an important parameter for several different applications: (i) it defines the lower edge of the wavelength transmission window of a material and therefore the shortest wavelength (λ 1 > hc E g ) that the material can be used for as an optical waveguide without suffering from high optical losses due to the absorption [see Fig. 1(a)]; (ii) for semiconductor photodetectors, it defines the longest wavelength (λ 1 < hc E g ) of detectable photons as the absorbed photons create free charge carriers (electron-hole pairs), which generate a current signal when the detector material is biased with a voltage [see Fig. 1 Fig. 1(b)]. In this fourth category, electrically driven coherent light emission and amplification are generally limited to direct bandgap materials [materials where the maximum of the valence band and the minimum of the conduction band have the same crystal momentum (k) in the Brillouin zone, e.g., GaAs and InP] such that photons can directly stimulate the emission of photons with the same energy and phase [see Fig. 1(b)]. For materials with an indirect bandgap [ Fig. 1(c)] [materials where the maximum of the valence band and the minimum of the conduction band have different crystal momentum (k) in the Brillouin zone, e.g., Si and Ge], while it is possible for photons to be absorbed by the generation of electron hole pairs via the generation of a phonon (heat), which makes up the momentum mismatch, it is not possible for a photon to directly stimulate another coherent photon in an indirect bandgap material as this would rely on the presence and absorption of phonons of the appropriate phase and momentum, but as phonons are incoherent and thermal in nature, such transitions are statistically rare. 23,24 High nonlinear optical coefficients are desirable for generating new wavelengths. The χ (2) optical nonlinearity enables nonlinear optical processes, such as second harmonic generation (SHG), sum frequency generation (SFG), parametric down-conversion (PDC), and difference frequency generation (DFG) 25 as well as cascaded processes that can emulate χ (3) nonlinear optical processes. 26,27 Such processes are particularly attractive for optical signal processing in communications 26,27 and the generation of entangled photon pairs for quantum optical applications. 28 χ (3) nonlinear optical processes, which are caused by the Kerr effect, include self-phase modulation (SPM), cross phase modulation (XPM), and four wave mixing (FWM). Nonlinear refractive index n 2 is used as a parameter for quantifying the Kerr nonlinearity of a medium. One of the most prominent uses of this nonlinearity at present is the generation of optical frequency combs by using micro-resonators. 29,30 Materials with a high electro-optic coefficient are important for applications that require fast manipulation of the optical wave's phase. Electro-optic materials exhibit the Pockels effect, which changes the refractive index of the material, when an electric field is applied. The refractive index change occurs without a change in the imaginary refractive index (no additional absorption). The instant changes to the refractive index and the ability to phase match the electrical wave with the optical wave to achieve traveling wave APL Photonics modulators make this process very attractive, and modulation speeds exceeding 100 GHz are feasible. 31,32 Most materials will also change their refractive index with temperature, and this characteristic is termed the thermo-optic coefficient. A large thermo-optic coefficient can be both an advantage and a disadvantage. For example, a large thermo-optic coefficient is attractive to tune ring resonators 33 or even as low speed optical modulators. 34 One the other hand, a large thermo-optic coefficient can result in significant changes in the behavior of the components on a PIC as the ambient temperature changes. If a PIC material has a relatively high thermo-optic coefficient and the stability of the PIC is very important, then the PIC will typically be packaged with an active temperature controller so that the functionality of the circuit is not impacted. This can introduce additional overhead in terms of size, weight, cost, and power consumption, which can make them less attractive for certain applications.
Some materials will deform mechanically upon application of an electric field, which is characterized by a piezoelectric coefficient. Piezoelectric materials are generally crystals that are noncentrosymmetric, including lead zirconate titanate (PZT), LiNbO 3 , AlN, and quartz among others. Mechanically deforming optical waveguides are attractive as it can be used to slightly change the length of a waveguide structure (e.g., ring resonator 35 ), which can be used for tuning. The piezoelectric effect in waveguide materials can also be used to generate acoustic waves, which enable device functionalities, such as acousto-optical modulators 36 and acousto-optical frequency shifters. 37 Extremely low optical propagation loss (0.14 dB/km 38 ) has been instrumental in the success of optical fibers, but it has only recently become possible to achieve low losses (dB/m) in PICs. Low losses can be important to maintain power budgets on transmission through a PIC; however, recently, losses have become sufficiently low to enable long optical delay lines on a chip with applications, including gyroscopes 39 and microwave photonics. 40 Ultra-low waveguide losses (dB/m) are also required for the integration of high-quality factor ring resonators that can be used for the efficient generation of optical frequency combs. 41 Table I lists some of the most commonly used optical waveguide materials together with the material properties as discussed above and common material technology parameters, such as mode size and waveguide losses, which enable us to compare different waveguide materials. We have also included two material technologies (GaAs and LiNbO 3 ), which had originally been demonstrated on native substrates (GaAs) or as a diffused waveguide (LiNbO 3 ), APL Photonics TUTORIAL scitation.org/journal/app but have recently been transferred as thin-films on SiO 2 (buried oxide, BOX), enabling the fabrication of optical waveguides with a much greater refractive index contrast and, therefore, smaller mode field diameters. For comparison, we included both the traditional waveguide structure and the thin film waveguide structure with buried oxide. From Table I, one can see that the waveguide materials have different strengths and weaknesses. For example, silicon is attractive for its very high refractive index and mature fabrication processes, but the small bandgap means that it can suffer from two photon absorption at moderate powers, which limits the power handling of the platform. Si 3 N 4 , on the other hand, offers ultra-low optical waveguide losses, which enable efficient optical frequency comb generation, but active components such as light sources, high-speed modulators, detectors, and amplifiers are not possible in Si 3 N 4 . Similar examples can be found for each of the materials. The conclusion is that no single material can address all the needs of complex PICs that require the integration of many different optical components with different functionalities, such as passive, active, and nonlinear on a single chip. Hence, there is a strong motivation to integrate different materials in PICs to increase the functionalities and use each material for what it is best for. The integration of different materials can be achieved by hybrid and heterogeneous integration, which will be discussed in more detail in Sec. III.

III. HYBRID AND HETEROGENEOUS INTEGRATION
The terms "hybrid integration" and "heterogeneous integration" are not always clearly distinguished in the literature, and sometimes, they are even used interchangeably. In this section, we aim to define these two distinct technologies and provide a brief introduction of the hybrid and heterogeneous integration processes. We also outline the differences between the two concepts and their advantages and disadvantages.

A. Hybrid integration
Hybrid integration is an integration process that connects two or more PIC or photonic device chips usually from different material technologies into one single package (see Fig. 2). This process is, in general, performed at the packaging stage after the fabrication of the PIC and photonic device chips. For example, hybrid integration has been used to integrate fully processed III-V devices, such as laser chips, 62-64 gain chips, 65,66 or even photodiodes, 67 onto silicon 68 and silicon nitride 69 PICs. The processed chips can be mounted either directly on the top of the PIC 62-67 or next to it. 70 The advantages of this integration technique are that one can test and characterize the device that needs to be integrated before the integration process. This enables to pick the best performing devices and discard non-functional components, which increases the yield and allows for tightening the performance control. 68 Moreover, due to the high flexibility of the integration process, it offers a path toward highly accessible automated production. 70 Hybrid integration is also very attractive for small scale production and bespoke circuits as the photonic elements that need to be integrated in the photonic circuit can be selected on a case by case basis. The disadvantage of hybrid integration is that the assembly for the hybrid integration method is usually larger, when compared to the heterogeneous APL Photonics TUTORIAL scitation.org/journal/app integration method. Furthermore, the photonic device alignment and integration process is a serial process (one device or one bar of devices at a time), which can be time consuming and can have limited throughput. This makes this process less attractive for PIC chips with extremely large quantities (such as might be required for low-cost mass market consumer electronics).

B. Heterogeneous integration
Heterogeneous integration is an integration process that combines two or more material technologies into a single PIC chip (see Fig. 2). This process is generally performed at the early-to midstages of fabrication of the PIC chip, for example, unpatterned III-V thin-films integrated onto pre-processed silicon photonic wafers. Heterogeneous integration 38 has been a field of intense research in recent years, particularly for the heterogeneous integration of III-V material into silicon [71][72][73][74][75][76] and silicon nitride 77 PICs. The key benefit of heterogeneous integration is that it can provide functionalities similar to monolithic integration, resulting in high alignment accuracy and low losses when transitioning between different waveguide material technologies. Other benefits are reliable performance of the integrated photonic elements and the low cost due to economy of scale. Therefore, it is suited for high-volume applications. 78 A minor disadvantage of heterogeneous integration is that it has stringent requirement of ultra-clean and smooth surfaces, which can be challenging in university research facilities. However, in semiconductor foundries, this is not an issue due to the dedicated and automated infrastructure and highly trained personnel. Another minor disadvantage of heterogeneous integration processes such as die-to-wafer bonding is that it does not allow for component-by-component modular testing before integration into more complex PICs. Thus, it is somewhat "all or nothing" with tight requirements on process control to improve the yield. Nevertheless, die bonding has been used for the majority of integrated photonic demonstrations.

IV. MATERIAL INTERFACING METHODS
The integration of different materials for hybrid and heterogeneous integration requires interfaces to transition from one material to another, as the refractive index and, therefore, the light guiding properties are different in each material. Generally, desired properties of these interfaces are that they have low loss, are tolerant to variations in the fabrication process, and should often operate over a certain wavelength range (e.g., the complete C-band). In the following, we will describe material interfacing methods that are commonly used for the hybrid and heterogeneous integration of different waveguide materials. In particular, we will describe grating coupling, mirror coupling, butt coupling, and adiabatic taper coupling.

A. Grating coupling
Grating coupling uses a periodic structure that is often etched into the waveguide material, creating a periodic grating of high and low refractive index regions, and can be used to couple light into or out of the PIC. The periodic refractive index structure creates a second-order Bragg grating, which, under normal conditions, couples the light vertically in and out. However, vertical coupling causes unwanted second-order reflection [79][80][81] and reduces coupling efficiency, which is why the period of the grating is adjusted in such a way that the coupling angle is tilted slightly off vertical, 80,82 as shown in Fig. 3 for a shallow etched grating coupler in the SOI technology. The Bragg condition for a diffraction grating coupler is where "nwg" denotes the effective index of the waveguide, "nc" denotes the cladding refractive index, "λ" denotes the wavelength, "Λ" denotes the period of the grating, and "m" denotes the diffraction order. 83 One should note that the perturbation from the grating affects the diffraction of light going to the top and the bottom, usually causing coupling losses that are larger than 3 dB as most of the light scattered to the bottom (approximately half) is lost. 83 However, the coupling efficiency can be increased by using specially designed grating couplers, such as slanted grating couplers, 80 chirped grating couplers, 84,85 grating couplers with an extra reflector, 86,87 and dual-layer grating couplers, 88-91 which enables coupling losses below 2 dB. 81,[92][93][94][95] The ability to couple light in and out of a PIC surface is usually used to interface optical fibers or fiber arrays with the PIC, enabling wafer-scale testing. It also provides the flexibility of placing the optical interface anywhere on the chip surface. 95 Moreover, it can also be used to interface the PIC waveguide material with materials that enable a different PIC functionality (see Fig. 4). For example, over a decade ago, the integration of InP/InGaAsP photodetectors was demonstrated on a SOI PIC by mounting the detectors (operation wavelength: 1.55 μm) on top of grating couplers and using a thick polymer (BCB) bonding layer. 97 In addition, light sources can be integrated by using grating couplers as demonstrated by Huihui Lu et al., showing the integration of a tilted-VCSEL above a grating coupler. 63

FIG. 3.
Illustration of a grating coupler in the SOI technology. 96 "Λ" denotes the period of the grating, "w/Λ" denotes the duty cycle of the grating coupler, "Θ" denotes the scattered angle of the grating coupler, "h" denotes the depth of grating teeth or etch depth, and "d" denotes the thickness of the BOX layer (SiO 2 ). An advantage of this integration method is that the required positioning accuracy of the detector/laser is lower when compared to other interfacing methods 98 as the beam diameter is usually in the order of ∼10 μm but can be controlled as required by adjusting the grating coupler design. Some of the limitations of this interfacing method are that it is challenging to achieve coupling efficiencies that are better than ∼2 dB (due to the grating coupler), the optical bandwidth of the grating couplers can be too narrow (∼58 nm for 3 dB FWHM), 99 and the coupling is polarization-dependent. 100

B. Mirror coupling
Another way to achieve a vertical coupling interface between two different material technologies is to use mirror coupling. The mirror couplers reflect light in/out of the waveguide by using an angled, highly reflective material interface that is fabricated in the waveguide plane. The angled material interface can be achieved by different means, such as mechanically polishing, 101,102 dicing blades, 101,102 and etching, 103,104 and the high reflectivity can be achieved by using metal coatings 105 or total internal reflection. 65,106 Figure 5 shows two examples of such mirror coupling schemes, which have so far mainly been employed to couple to optical fibers; however-similar to grating couplers-these mirrors can also be used to vertically couple two material technologies with each other, as explained by Noriki 102 et al. and Song 65,107 et al. They used a chemically assisted ion beam etched mirror interface to redirect the propagating light from a semiconductor optical amplifier waveguide into a SOI PIC with the help of a grating coupler in the silicon layer. 65,107 Mirror coupling as an interfacing method has some advantages, when compared to grating coupling as a vertical interfacing method. For example, mirror coupling does not suffer from the limited wavelength bandwidth of grating couplers and can, in principle, achieve higher coupling efficiencies as they do not suffer from the diffraction of light into the substrate. However, the mirror interfaces are usually more difficult to fabricate as they require additional fabrication steps, and depending on the fabrication method, they may only be achievable at the chip end facets.

C. Butt coupling
Butt coupling is commonly used to interface fibers with PIC chips, but it is also an attractive method to interface two different PIC material technologies. Butt coupling has its name from the coupling process, which requires the butting of the two devices to be interfaced in a way that enables the coupling of the mode field of the transmitter to the receiver device. 108 The coupling efficiency depends on several factors: 108 (1) the quality of the end facets, (2) the angle at which light is reflected back from the end facet, (3) the spatial misalignment of the modes, and (4) the matching of the modes in the two material technology interfaces. (3) and (4) are usually calculated together by using the overlap integral. 108 Butt coupling was demonstrated by Urino et al. 109 and Mack et al., 110 who co-packaged a III-V laser diode interfacing with a silicon photonic PIC, 110 as shown in Fig. 6. They did hybrid integration of the laser with a Si PIC comprising modulators and PDs  Butt coupling is attractive as it is not very sensitive to different polarizations and operates over a very broad range of wavelengths. Furthermore, very high coupling efficiencies can be achieved by this coupling method as the mode sizes at the interfaces can be matched very well and scattering and reflection channels can be reduced by appropriate designs. 121 However, it also has some drawbacks, such as it is very sensitive to misalignment as the mode size is usually quite small; therefore, small misplacements can cause a significant reduction in the coupling efficiency. It also possesses stringent requirements for the coupling facet 122 (smooth interface), and the interfaces may cause undesired strong back reflections.

D. Adiabatic tapers
Adiabatic tapers are optical waveguide structures that slowly vary their dimensions (most commonly, the waveguide width) to adiabatically transition the guided waveguide mode from one material technology to the other. Changing the width of the waveguide influences the effective refractive index of the waveguide mode, which is used in adiabatic taper transitions to achieve a smooth transition of light between the two materials.
Such adiabatic tapers have successfully been used to transition between many different waveguide material technologies (see Fig. 7). Examples include adiabatic tapers between Si 3 N 4 and LiNbO 3 waveguides with transition losses as low as 0.9 dB, 123 between Si 3 N 4 and GaAs with transition losses below 1 dB, 27 and between Si and Si 3 N 4 with transition losses as low as 0.5 dB. 124 Such transitions can also be used to interface with lasers and detectors. For example, Lamponi et al. explored and used inverted adiabatic tapers for heterogeneously integrated InP/silicon-on-insulator (SOI) laser sources (evanescently coupled hybrid lasers), achieving a 90% coupling efficiency for a taper length of 100 μm. 125 Similarly, Wang et al. 98 used adiabatic tapers for a heterogeneously integrated InP/silicon photodetector and achieved 1.6 A/W responsivity at 2.35 μm.
The advantages of adiabatic tapers are that they offer a way to achieve extremely low loss, broadband, and fabrication tolerant transitions between different waveguide technologies. For example, the alignment tolerances of adiabatic couplers can be in the order

TUTORIAL
scitation.org/journal/app of 1 μm, 128 which makes this interfacing method very robust. A systematic study investigated grating coupling, butt coupling, and adiabatic coupling when transitioning between GeSbS and Si singlemode waveguides and found that out of the three interfacing methods, adiabatic coupling offers the lowest coupling losses (0.7 dB) and negligible back-reflections. 129 A downside of adiabatic tapers can be that they require a larger footprint (100s of micrometers) when compared to grating coupling and butt coupling. The larger footprint is required as the adiabatic change in waveguide width means that the taper needs to have a certain length in order to change the width sufficiently slowly to transition the waveguide modes efficiently. Another issue of taper couplers can be that the tip width of the taper is limited due to fabrication limitations, which may cause undesirable reflections and that it can be difficult to transition between waveguide materials that have a large difference in their respective refractive indices.

V. INTEGRATION METHODS
Having considered how optical components can be interfaced between different material platforms, we must now consider how these different material platforms can be co-integrated and how the devices can be aligned. In this section, we provide an overview of different integrations methods that are commonly used for hybrid and heterogeneous integration for PICs. In particular, we describe flipchip, die and wafer bonding, transfer printing, and the direct growth and deposition integration methods (which is rather a monolithic integration approach). Several of these integration methods can also be combined to achieve PICs that require the integration of several material technologies.

A. Flip-chip integration
The flip-chip integration technique (also known as controlled collapse chip connection) is a method to integrate and interconnect manufactured chip dies to a carrier wafer or package substrate using bumps of electrically conducting material for the adhesion and electrical connection and was first developed by IBM 60 years ago. 130,131 In the integration process, the chip surface with the electrodes is flipped or put face down on the carrier substrate. 132 This integration method was developed for the integration of electronic circuits and matured over the course of the electronic circuit revolution. However, in recent years, this integration method has also attracted attention for the integration of optical components in photonic integrated circuits. 130,131 In the following, we will provide a brief overview of this integration method and how it has been used for hybrid integration in PICs.
The flip-chip technique requires metal electrode pads on the surfaces of the chip die and the wafer/larger chip that will be bonded together. The pattern of the pads on the die and wafer surface matches each other's or is mirrored when viewed from the top [see Fig. 8(a)]. These electrodes are then interfaced to each other using "bumps" of solder or other metals, which are liquefied and wet between the electrodes on the two surfaces [see Fig. 8 The fabrication process for creating the mirrored electrode pads (also referred to as "under-bump metallization") often uses metal deposition methods, such as sputtering, plating, or evaporation. The under-bump metallization is important as it provides a strong adhesion interface between the die bond pad and the bump metal, provides a low electrical resistance contact between the chip and the bump metal, and prevents the diffusion of the bump material into the chip, which can be undesired. 131,134 After the under-bump metallization is completed, the bump is deposited on the bonding pads of the chip. The bump material is commonly a low melting point solder such as lead/tin, tin/copper/silver, or gold/tin, and it can be deposited by plating, stencil printing, laser dispense, or mold transfer. 131 In cases where very high frequency operation is required, the bumps can also be pure gold deposited using a ball-bonder from gold wire. 135 The last step of the flip-chip integration technique is to bring the top chip in contact with the substrate and melt the solder bumps by using thermocompression, thermosonic, or adhesive (isotropic, anisotropic, and nonconductive) flip-chip joining methods. 130 The surface tension and the gravitational force of the molten solder can create a force on the chip that centers the bonding pads, which is also called a self-alignment phenomenon [as illustrated in Fig. 8(b)]. 131,133 Common advantages of the flip-chip integration method are that it is a very mature process (has been developed for decades), it allows for good thermal management of the integrated dies, 132,136 the footprint of the contacts is small, 131 it increases the integration density, 137 it is a low-cost process, dies can be tested/characterized before assembly, and it increases the yield. 138 Furthermore, the APL Photonics TUTORIAL scitation.org/journal/app electrical contacts have a low parasitic inductance and short interconnect length, making them suitable for high-frequency signal transmission, i.e., tens of GHz. 139 The mature flip-chip integration process also makes this method attractive for the integration of optical components in PICs. An example is the cost-effective hybrid integration of a lasersource on a silicon photonic integrated circuit, as demonstrated by Lu et al. 63 in 2016. They bonded a VCSEL diode on top of a grating coupler and optimized the tilt angle to achieve low coupling losses [see Figs. 4(a) and 4(b)], resulting in an insertion loss of 11.8 dB. 63 Flip-chip integration can also be used for achieving waveguide-to-waveguide interfaces via butt coupling. The precision alignment for this integration is achieved by using solder aligned photonic flip-chip assembly [see Fig. 9(a)], as demonstrated by Barwicz et al., 140 including vertical and lateral mechanical stops, which resulted in a minimum transmission loss of 1.1 dB over a 100 nm spectrum. Flip-chip integration is best suited to interfacing relatively large chips together. In cases where much smaller chips or more intimate contact is required, other techniques should be considered.

B. Transfer printing
Micro-Transfer Printing (μTP) is a versatile micro-assembly technology, which provides deterministically fast and precise assembly of microscale components from their native substrates onto nonnative substrates with the help of an elastomer stamp. [142][143][144] This integration method was invented in 2003-2006 by Rogers et al. 145,146 and commercialized in 2006 by Semprius 142 and X-Celeprint. This assembly method has been used to transfer a range of materials and devices, such as inorganic semiconducting materials, organic materials, functional polymers, metals, piezoelectric materials, photodetectors, sensors, filters for CMOS cameras, and MEMS. [142][143][144]147 In the following, we will focus on the use of this assembly method for integrating photonic components on PICs. An extensive overview of this integration method can be found in Ref. 148.
The basic principle of the micro-transfer printing procedure is shown in Figs. 10(a) and 10(b). The transfer process requires a pickup and printing step and uses a viscoelastic material [polydimethylsiloxane (PDMS)] as a stamp. In the first step, prefabricated functional devices on their native substrate are picked up by adhering to the stamp upon contact. [142][143][144] The pickup step requires that the energy release rate of the device-stamp interface is larger than that of the device-substrate interface, which can be achieved by using high speed stamp movements. 142,147 The fast stamp movements result in the adhesion of the device to the stamp, which can then be used to transfer the device to a non-native substrate for integration. In the printing step, the stamp is brought in contact with the non-native substrate and the stamp is moved out of contact slowly, 143,147 completing the printing process. The slow movement speed results in a smaller energy release rate of the device-stamp interface, when compared to the device-substrate interface. 142,147 Micro-transfer printing has successfully been used to integrate a range of active optical components on passive optical device layers. One of the first demonstrations in 2012 was the membrane reflector (MR) surface-emitting laser on silicon that is based on a multilayer semiconductor nanomembrane, 149 which was quickly followed by the transfer printing of diodes 150 and the integration of single-mode waveguide-coupled III-V-on-silicon broadband light emitters. 73 [To interface the transfer printed optical devices with the waveguides, grating couplers, 153 adiabatic tapers, 154 and butt coupling 153 have been explored, where adiabatic tapers are particularly attractive for lasers and amplifiers due to the low interface loses, grating couplers are attractive for detectors as the PICs can be characterized beforehand with the same grating couplers, and butt coupling because of the good thermal contact with the silicon substrate (Fig. 11).] Since then, the integration method has enabled the integration of high-quality DFB lasers, 151 semiconductor optical amplifiers, 73,152 modulators, and detectors 153 onto SOI.
Micro-transfer printing has matured significantly over the years. It can transfer multiple active and passive components onto non-native substrates with high precision ±1.5 μm (3 sigma), high speed (30-40 s), 155 and high transfer yields that exceed 99%. 147,156 Furthermore, the stamps used for the transfer have a long lifetime of more than 300 000 printing cycles. 155 Similar to the flipchip technique, micro-transfer printing allows-in some cases-for pretesting of the fabricated devices prior to integration on the target wafer. 155 However, in contrast to flip-chip bonding, micro-transfer printing is best suited to transferring very small elements-even at the scale of individual devices onto a large substrate. Furthermore, the transferred "chiplets" are generally between 0.2 and 3 μm thick, and hence, it is possible to conduct transfer printing midway through fabrication of the PICs, planarize the surface after the chiplet has been transferred, and proceed with additional

C. Die and wafer bonding
Die and wafer bonding is a process of joining a die/wafer to a wafer to form a permanently bonded stack. This process is particularly attractive when large area films are required with excellent material properties (e.g., crystalline materials that are difficult to grow on non-native materials). The bonding process has been developed for the electronic integrated circuits and MEMS industries, and bonding tools (commonly called wafer bonders) are commercially available from most micro-/nano-fabrication equipment suppliers. 158 Wafer bonders consist of wafer-handling stack and a pair of chucks for applying heat, voltage, and force to the wafer stack. The whole setup is usually placed in a chamber to control the atmosphere during the bonding process (typically, vacuum to avoid trapping of air), as illustrated in Fig. 12(a). 158 Different wafer bonding methods have been developed over the years, and they can be categorized depending on the bonding mechanism, namely, without intermediate layer bonding and intermediate layer bonding, as illustrated in Fig. 13(b). 159,160 Bonding without an intermediate layer describes the method to join two surfaces together without using an adhesion layer in between, and the most commonly used bonding method for PICs 162 in this category is the direct bonding [see Fig. 13(a)]. Direct bonding has been used since 1960 for many substrates and structures. [163][164][165] A breakthrough for the direct bonding technique was the demonstration by Lehmann et al. in 1989 and bonding III-V semiconductor layers, such as GaAs and InP, on the bare silicon bubble free. 166 The bonding strength of this method can be very high, enabling the further processing of the wafers and even mechanically grinding and polishing the bonded dies/wafer. Furthermore, direct bonding provides an excellent thermal conductivity between the bonded film and the target wafer, 161 which is very attractive for the thermal management of the integrated devices. The yield of integrated devices can be very high when using the direct bonding integration method; however, it has stringent requirements on the surfaces, which need to be extremely clean and ultra-flat. 159,167,168 If the surfaces are not carefully prepared, the bond may suffer from issues such as outgassing, trapped particles, and a weak bond. 168,169 When using direct bonding at high-temperature (e.g., annealing at 600 ○ C 170 ), one also needs to consider the thermal expansion coefficients of the materials that will be interfaced as the thermal mismatch can create stress, which may be detrimental to the bond and, therefore, for the integrated devices. 161 However, the O 2 plasma assisted (SiO 2 covalent bonding) method can achieve a high bonding strength even for a low-temperature annealing process (<400 ○ C). 171,172 The most commonly used intermediate layer bonding method for PICs is adhesive bonding by using polymers such as BCB and SU-8 as an adhesion material. 160 For the bonding process, the polymer layer is spin coated on the target wafer followed by a soft bake to remove any solvents (as they can create bubbles) and then brought into contact with the dies/wafers that will be integrated on the target wafer and finally perform a thermal annealing step [see Fig. 13(b)]. 173 When compared to the direct bonding method, the intermediate layer bonding imposes far fewer restrictions on the roughness and cleanliness of the surface; 158,160 in fact, the spincoating of the polymer can be used to fill gaps and provide a flat surface. Furthermore, intermediate layer bonding offers a high bonding strength at moderate temperatures (∼250 ○ C), low bonding induced strain, and good uniformity and scalability. 173 However, one potential disadvantage of the intermediate layer bonding when using polymers is that the thermal conductivity of the layer is quite low, which can make the thermal management of devices difficult. However, typically, in a PIC context, the thermal resistance of the integrated devices is determined by the buried oxide layer and not the adhesive bonding layer.
Both bonding methods (direct bonding and intermediate layer bonding) have enabled the integration of several optical components on PICs 174 (see Fig. 14). A large effort of this work was the integration of III-V materials on silicon waveguides, enabling the integration of lasers, 175 modulators, 176 amplifiers, 177 and detectors. 178 However, wafer bonding is also a very attractive method for integrating high quality material films on waveguides, such as magnetooptic materials 179 and nonlinear optical materials, 25 enabling PICs with a wide variety of useful functions, properties, and high performance. 180 For example, wafer bonding can be used to produce vertically integrated circuits using a crystalline Si layer on the top of an ultra-low loss silicon nitride (SiN) waveguide layer; 181 the integration of crystalline magneto-optical materials [yttrium iron garnet (Ce:YIG)] for nonreciprocal devices, such as optical isolators and circulators; 180,182 and nonlinear and electro-optical materials, such as LiNbO 3 . 123 Furthermore, in 2019, Hu et al. demonstrated a novel photonic integration method of integrating III/V (MQW lasers) materials into the SOI substrate by regrowth on a bonding template. This unique process combines the advantages of both monolithic growth and wafer bonding approaches. 183 A similar approach is followed by NTT, resulting in high-performance III-V membrane devices integrated on silicon waveguide circuits. 184

D. Layer deposition
Layer deposition is a monolithic integration process, where thin films of materials are deposited on the target wafer. In general, one can differentiate between two categories of deposition processes: APL Photonics TUTORIAL scitation.org/journal/app (i) physical vapor deposition (PVD) and (ii) chemical vapor deposition (CVD). A list of different deposition methods for the two categories is given in Fig. 15. Physical vapor deposition is a vacuum deposition process in which the co-deposited material undergoes a transition from the solid state at a source to a gaseous state that is directed to the target, and at the target surface, it condenses to form a solid state, resulting in a thin film. Chemical vapor deposition describes processes that expose target wafers to volatile precursor gases, which react and/or decompose on the target to form a high-quality thin film of the desired material. In general, each of the different deposition methods has its advantages and disadvantages and is suitable for the deposition of a range of materials. In practice, the material that is desired for integration defines the deposition method to enable the deposition of high-quality thin films on target wafers. One of the main restrictions when such deposition methods are used to integrate materials on PICs is that the processing temperature in most cases should not be too high. Depending on the PIC material technology, it is required that the processing temperature stays below the dopant activation temperature for Si modulators (1030 ○ C) or the thermal budget used for dislocation control of Ge-on-Si photodiodes (825 ○ C). When applied in the back-end, it is important that the processing temperatures stay below ∼450 ○ C. Another important property of the deposition process is the conformality of the deposited layer. The conformality is, generally speaking, lower in PVD processes, when compared to CVD processes, as the directionality of to-deposited material is very high (particularly, in the case of evaporation). A detailed description of the different deposition methods would be too long for this tutorial; hence, we recommend Ref. 185 for further information and focus in the following on examples of materials that can be deposited using some of the deposition methods that are attractive to integrate additional functionalities into PICs. Highly efficient nonlinear acousto-optic waveguides can be integrated on silicon waveguides by depositing chalcogenide glasses using e-beam evaporation. 186 Chalcogenide glasses, such as As 2 S 3 , GeSbTe, and AgInSbTe, are attractive for acousto-optical applications (e.g., stimulated Brillouin scattering) as they can confine acoustic modes even when a SiO 2 buffer layer is used. 187 Furthermore, chalcogenide glasses have a broadband infrared transparency (0.8-20 μm) 188 and high third order nonlinearity, 189 which make chalcogenide waveguides attractive for mid-IR applications, 187,190,191 optical frequency comb generation, 192 supercontinuum generation, 193 and wavelength conversion. 194 Si 3 N 4 is an attractive material for integration on PICs as it enables optical waveguides with low optical losses, which are attractive for routing optical signals over longer distances on chip and for high Q-factor nonlinear optical microresonators. 195,196 Different deposition methods have been explored for the deposition of highquality Si 3 N 4 films, where low pressure chemical vapor deposition allows ultra-low loss waveguides 195 if processing temperatures of >700 ○ C can be tolerated by the PIC; for lower temperatures (inductively coupled), plasma enhanced chemical vapor deposition 197 and sputtering 198 are attractive achieving waveguide losses below 0.5 dB/cm.

E. Direct growth
Direct growth is another monolithic integration process. The difference in the deposition processes outlined above is that direct growth is an epitaxial process in which crystalline layers are grown, which is a very attractive way to integrate semiconductor materials in a scalable manner. Crystalline growth is particularly important for electro-optic active devices, such as lasers, amplifiers and detectors, as defects and dislocations can be detrimental to the device performance and lifetime. A challenge in reducing such defects is to overcome crystal lattice mismatch between different materials. For example, the lattice mismatch between GaAs and Si is around 4.1%. 201 This can cause structural defects during the growth, which can occur in different sizes and ranges from 0D point defects (such as vacancies or interstitials), over 1D line defects (such as misfit dislocations), and 2D planar defects (such as stacking faults, twin defects, misfit dislocations, and grain boundaries) to 3D defects (such as voids and precipitates). Another challenge can be the significant differences in the coefficient of thermal expansion 202 between different Germanium is a very attractive material for photodetectors on silicon photonic integrated circuits. Germanium photodetectors can be epitaxially and selectively grown by Reduced Pressure Chemical Vapor Deposition (RP-CVD) in a silicon recess. 119,203 This process is also available in current silicon photonic foundry processes. The germanium film is grown at 730 ○ C on a germanium buffer layer, which reduces the misfit dislocations and keeps the surface of the grown germanium layer smooth. 119 Experimental demonstrations include photodetectors with a responsivity of 1 A/W at a wavelength of 1.55 μm 119,203 and a bandwidth of >67 GHz at 1 V reverse bias. 204 The growth of III-V materials on silicon is also very attractive as it enables the integration of lasers, amplifiers, modulators, and detectors on material technologies, such as SOI (see Fig. 16). In recent years, there has been a considerable progress in this field, demonstrating the direct epitaxial growth of bufferless 1.5 μm III-V lasers by metal organic chemical vapor deposition (MOCVD) onto one of the standard SOI wafers with a silicon film thickness of 220 nm. 205 When growing pure InP, lasing can be achieved at the room temperature, emitting a wavelength of 900 nm. When embedding InGaAs quantum structures inside InP, the lasing wavelength can be shifted to the desired communication wavelength of around 1500 nm. 205 In addition, GaAs-based ridge lasers operating at an ∼1000 nm wavelength have been demonstrated. 184 Photodetectors can also be directly grown on SOI without the need of a buffer layer, enabling the demonstration of a photoresponsivity of 1.06 A/W at 1.55 μm with an operating range from 1.45 to 1.65 μm. 206

VI. HYBRID AND HETEROGENEOUS INTEGRATION EXAMPLES FOR REAL WORLD APPLICATIONS
In this section, we provide an overview of three examples that highlight and show the power of hybrid and heterogeneous integration approaches to achieve PICs with outstanding properties that would not have been possible in a single PIC material technology.

A. Transceivers
The transceiver market for data centers is driven by the rapid growth of the Internet. Ideally, transceivers should have a high data capacity, while they should be pluggable (small size) with low power requirements. Furthermore, the price of transceivers should be as low as possible, which requires a scalable technology with production volumes in the multimillion per annum. 208 Arguably, the most attractive material technology for scalability and with potential for low prices is silicon photonic technology. However, the lack of light sources requires hybrid/heterogeneous integration approaches to achieve the required functionalities on silicon.
Transfer-printing-based integrated photodetectors have been used for transceivers, such as the experimental demonstrations of a silicon photonic transceiver array (four channels) by Zhang et al. 153 [ Fig. 17(a)]. They showed that transfer printing integration technology is suitable to integrate O-band III-V photodiodes, and by choosing a cutoff wavelength of 1.37 μm, it was possible to realize a duplexing of the upstream (1310 nm O-band) and downstream (1550 nm C-band) signals. An example of a recent demonstration using die-to-wafer bonding is the III-V/Si transceivers with integrated DFB lasers, Mach-Zehnder modulators, and wavelength multiplexer for the transmitter, which has been demonstrated and commercialized by Intel. The III-V heterogeneous integration can be done on 300 mm wafers, and the technology is enabling fiber communication up to 10-km reach with data rates of 100 Gb/s [ Fig. 17(b)]. 209

B. Integrated optical gyroscopes
Precision positioning and navigation are forecasted to be a rapidly growing market, which is driven by autonomously driving cars and drone applications, among others. For such applications, the efficient use of space, weight, and power is very important. Technological devices that promise to address such navigational needs are integrated optical gyroscopes. The anticipated production value for such integrated optical gyroscopes systems is estimated to be $20 × 10 6 per annum by 2025. 210 Similar to transceivers, such high production numbers make it attractive to utilize heterogeneously integrated III-V materials on silicon photonic circuits as a material technology. In the following, advances toward such systems are provided.
For instance, John Bowers' group in 2017 demonstrated a heterogeneously integrated optical engine for interferometric optical gyroscopes (see Fig. 18). In this engine, all the active and passive components (a Fabry-Perot multi-mode laser, photodiodes, phase modulators, and adiabatic 3-dB splitters) except the sensing coil were fabricated on a chip within a 0.5 × 9 mm 2 area. Using a 180-m-long polarization maintaining fiber (PMF) with 200 mm diameter as a sensing coil, a minimum measurable rotation rate of ∼0.53 ○ /s (1908 ○ /h) was achieved. 211,212 To replace the bulky fiber coil, they also investigated the integration of a waveguide coil by utilizing ultra-low loss (<0.78 dB/m) SiN waveguides, which resulted in a theoretical bias instability of 58.7 ○ /h. 213 Although this result is much higher than fiber optic gyroscopes, which can reach bias instabilities of 0.0001 ○ /h and below, 214 there is a huge potential to further improve the integrated gyroscopes, making them competitive for the market segment that is currently dominated by using MEMS sensors. Furthermore, replacing the sensing fiber coil with an on-chip waveguide coil (or resonator) will not only shrink down the size but also make it less sensitive to vibration and shock, [211][212][213] which MEMS sensors are sensitive to.

C. Optical frequency synthesizer
Another excellent example of the power of hybrid and heterogeneous integration is the recent demonstration of an optical frequency synthesizer by using integrated photonics (see Fig. 19). 1 This demonstration required the integration of several optical material technologies in order to utilize each material's strengths: (i) Heterogeneously integrated III-V lasers on silicon photonic waveguides to achieve tunable narrow linewidth lasers; (ii) ultra-high quality factor silica toroid for the generation of a narrow spaced optical frequency comb (22 GHz); (iii) high-quality factor silicon nitride microresonators for the generation of an octave spanning frequency comb with a wide spacing (∼1 THz); (iv) GaAs (or LiNbO 3 ) for frequency doubling the ∼2 μm comb line, generating ∼1 μm wavelength, which is beating with a 1 μm wavelength comb line; and the beat frequency is detected by using (v) high speed III-V photodetectors. Using a combination of hybrid and heterogeneous integration technologies to combine these elements together enabled the demonstration of an optical frequency synthesizer that can be programmed by a microwave clock across 4 THz with 1 Hz resolution and is exceptionally stable across this region with a synthesis error of below 7.7 × 10 −15 . 1 Achieving such an outstanding performance in a small package has potential to disrupt research fields such as ultrafast science and metrology, 1 data transmission, 215 physical sensors, 216 and quantum photonics. 217

VII. FUTURE DIRECTIONS
Hybrid integration and heterogeneous integration enable the integration of an increasing variety of active and passive optical components on photonic integrated circuits. By their nature, active integrated photonics require electrical contacts for the generation, manipulation, and detection of the optical signals, and indeed, the primary motivation for the industrialization of integrated photonics is to relieve the electronic input/output bottleneck; hence, the cointegration with electronic chips within a single package is already being pursued with appropriate interposers. 20 We believe that as the hybrid approaches for mass manufactured transceivers mature, there will be a new wave of densely integrated hybrid photonic chips deployed across a wider variety of applications. One of the main developments that we foresee is the integration of more exotic materials on photonic integrated circuits. For example, 2D materials have very attractive materials properties that enable the generation, manipulation, and detection of light. 218 Hence, 2D materials will become more attractive over the next few years as the fabrication maturity and control of the material properties increase rapidly. We also believe that there will be a strong push for interfacing photonic integrated circuits with free space optics. Such technology is currently pursued for LIDAR applications, but in the future, one can also image that a similar technology can be used to probe atomic transitions in on-chip vapor cells 219,220 or manipulate ions in complex ion traps. 221,222 Furthermore, with the emergence of scalable techniques such as micro-transfer printing, in combination with ever improving direct-write maskless approaches, it is conceivable that quite complex hybrid circuits could be "printed" digitally and on demand. This would enable low-cost prototyping and even low volume manufacture of photonic chip products tailored to the specific needs of even quite niche customers. This would lead to an explosion of new applications and opportunities.

VIII. CONCLUSION
The maturity of hybrid and heterogeneous photonic integration technologies is accelerating rapidly, enabling photonic integrated circuit devices with unprecedented functionalities and a reduction in device size, weight, power consumption, and cost. Furthermore, hybrid integration onto a single substrate also provides the additional benefit of increased robustness and potentially more scalable automated manufacture than comparable systems assembled from discrete components. The motivation behind the hybrid and heterogeneous integration for photonic integrated circuits is to use each material according to its strengths featured by the material properties. As an introduction into this field, we provided an overview of some of the most common photonic integrated materials, hybrid and heterogeneous integration concepts, photonic interfaces to transition between the different materials, different integration methods, hybrid and heterogeneous integration examples for real world applications, and an outlook into the future of these technologies in this Tutorial.
We strongly believe that the future of photonic integrated photonics requires photonic circuits that use different material technologies, as the complexity and the requirements for photonic integrated circuits grow with the applications that it enable. Hence, we foresee a bright future of hybrid and heterogeneous photonic integrated circuits with mass production applications, such as highspeed communications and eventually computing. We also anticipate that as this technology matures, it will enable economically viable manufacture of hybrid chips for lower volume niche applications, such as microwave photonics, quantum photonics, precision sensing, metrology, and spectroscopy among many others.