Simplified Josephson-junction fabrication process for reproducibly high-performance superconducting qubits

We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with $T_1$ relaxation times averaging above 50$~\mu$s ($Q>$1.5$\times$ 10$^6$). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type (PICT) junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. In a study of more than 3600 junctions, we show an average resistance variation of 3.7$\%$ on a wafer that contains forty 0.5$\times$0.5-cm$^2$ chips, with junction areas ranging between 0.01 and 0.16 $\mu$m$^2$. The average on-chip spread in resistance is 2.7$\%$, with 20 chips varying between 1.4 and 2$\%$. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7-2.5$\%$. We show that 60-70$\%$ of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.


INTRODUCTION
Superconducting quantum circuits constitute a promising architecture for the realization of quantum computers. Over the past two decades, many researchers have put strong effort into improving the fabrication processes of superconducting circuits to increase the achievable quantum-coherence time. [1][2][3] On the other hand, the reproducibility of Josephson-junction (JJ) fabrication has only recently gained considerable interest, motivated by the need for a scalable process to engineer multiqubit systems. [4][5][6][7][8][9][10][11] Variation of the Josephson inductance represents the dominant cause of qubit-frequency variation, e.g. for the transmon-type qubit. 12 An increased reproducibility of JJs is therefore important to ensure predictability of qubit frequencies, in order to enable pulsed-microwave control while avoiding cross-talk, a necessity for scaling up beyond a few coupled qubits. [13][14][15] Reproducibility is also important for other superconducting devices, particularly the traveling-wave parametric amplifier (TWPA), [16][17][18][19][20][21] which requires impedance matching and identical inductances along the long, lumped-element transmission line to avoid reflections and signal loss.
The all-dominant materials combination of JJs for qubit applications consists of an aluminum/aluminum oxide/aluminum (Al/AlO x /Al) sandwich fabricated by double-angle shadow evaporation of aluminum, within one vacuum cycle, with controlled in-situ oxidation inbetween to form the tunneling barrier. 22,23 Maintaining a galvanic, superconducting contact between the JJ's eleca) Electronic mail: amr.osman@chalmers.se trodes and the rest of the circuit is important, in order to avoid forming "parasitic" junctions in series, whose dielectric loss tangent contributes to decoherence and parameter fluctuations. 1,24 In fact, Lisenfeld et al. 25 found, in a recent study, that 40% of the two-level-system (TLS) defects responsible for dielectric loss were located within the parasitic junction formed due to the shadow evaporation technique (with the remaining 60% located at circuit interfaces and almost none within the JJ itself). Additionally, Nersisyan et al. 2 showed that the area of this parasitic junction adversely affects the coherence of the qubit. To mitigate this issue, the parasitic junction can be eliminated by depositing a patch (or bandage) layer that connects the junction electrodes to the rest of the circuit, after removal of the native oxide of aluminum. 26 However, the further processing introduced by adding the patch can introduce more losses, especially those caused by interfacial resist residues that are difficult to remove. 27 In this work, we propose and demonstrate a new technique to fabricate both the junction and the patch layer in a single lithography step by evaporating from three angles. We name the technique patch-integrated crosstype (PICT), with reference to the cross-type Josephson junctions first proposed in ref. 23. We favorably evaluate the quality and reliability of our process by characterizing both the qubit coherence and the fabrication reproducibility. We measured the T 1 relaxation and T * 2 Ramsey free-induction decay times, and their fluctuations, showing an average quality factor of 1.6 × 10 6 , i.e. without additional losses in comparison to our standard fabrication process. 28 In addition, we characterized the reproducibility of the JJ parameters by fabricating a statistically significant number (> 3600) of Josephson junctions and measuring their normal resistance, R N , at room temperature. R N is directly proportional to the Joseph- son inductance, L J , and therefore, the measurement of R N provides information on reproducibility of the qubit frequency, f 01 . 9,12,29 The measured inter-chip variation is 3.7% across a wafer, which drops to an average onchip value of 2.7%. Furthermore, the resistance spread increases with decreasing junction size: for sizes used in fixed-frequency transmon qubits (0.02-0.06 µm 2 ), we found a wafer-level variation of 3.4-4.9%, corresponding to 1.7-2.5% in qubit frequency.

METHOD
The process described in this work builds on the background of our previous standard qubit design and fabrication techniques. 28 The layout of a typical device is shown in Fig. 1(a): it consists of a transmon/Xmon-type qubit 12,30 (i) that is capacitively coupled to a readout resonator (ii), which is inductively coupled to a transmission line (iii). In our standard fabrication process, 28,30 the aluminum ground plane is first deposited using electron beam evaporation. The wiring (transmission line, resonator, and shunt capacitor) and the flux trapping holes are then patterned using optical lithography and etched using wet chemistry. Figure 1(b) shows the JJ layout and the bandages or patches commonly used to connect it to the rest of the circuit. 26 The junction itself (A) is patterned using electron beam lithography (EBL), followed by the cross technique to deposit the Al layers 23 (two thin-film depositions at an angle separated by a 90 • planetary turn, and oxidation to form the tunneling barrier), in a Plassys MEB 550s evaporator, followed by liftoff. Next, the patch layer (B) is patterned in a final lithography step, which ensures galvanic connection of the junction to the capacitor (C) and the ground plane (D). After development, the oxide layer on top of the aluminum is milled in-situ before the deposition of the patch and lift-off.
In our PICT process, we pattern both the junction and the patch in one EBL step and evaporate the thin films within one vacuum cycle. A modification to the patch layout makes this possible, as shown in Fig. 2, where in- stead of rectangles, the patches are shaped like 45 • fringes to provide selective deposition and milling when the resist is thick enough. This eliminates an entire lithography run and reduces the total steps of Josephson-junction fabrication by 50%.
The subsequent evaporation steps are shown in Fig. 2(a-e), where θ and ϕ are the planar and tilt angles (from the y-axis) of the sample holder, respectively. The evaporation and ion milling are both perpendicular to the yz-plane, pointing towards the -x direction. The reference position is shown in Fig. 2(a), where ϕ = θ = 0 • . When the angles are set at θ = θ 1 and ϕ = ϕ 1 , first, the sample holder turns counter clockwise around the x-axis by θ 1 degrees in the yz-plane. Next, the sample holder turns (tilts) around the z-axis by ϕ 1 degrees.
The first junction electrode (1) is deposited at θ = 0 • and ϕ = 45 • (Fig. 2(b)) and oxidized to form the tunneling barrier. The second electrode (2) is then deposited at θ = −90 • and ϕ = 45 • in Fig. 2(c) and oxidized to form a protective layer for the Al film; this controlled oxidation is preferred over natural oxidation of aluminum as a result of exposure to the ambient. The purpose of the two slits in both the ground and capacitor electrodes, into which the two junction electrodes fit, is to avoid any discontinuity in the deposited electrodes due to shadowing. Having slits is not a general necessity; we added them to keep the electrodes and the wiring layout as close as possible to the design of our standard devices. Next the surface is prepared for patching, i.e. removing the oxide atop the Al films in the fringes. This is achieved by Ar + ion milling of the substrate at θ = −45 • and ϕ = 45 • (Fig. 2(d)). At this angle, the resist wall protects the junction area from being milled away. Al is then deposited from the same angle in order to form the patch ( Fig. 2(e)). The Al is anew oxidized to create a protective oxide. Figure 2(f) shows a scanning electron micrograph (SEM) of the junction and the patch after lift-off.
Apart from ϕ and θ, three other parameters have to be taken into account in this process: 9 the resist thickness s, the width of a fringe f , and the width of the junction electrodes d. The cross-type technique requires that s > d tan ϕ to obtain selective electrode deposition 23 (3D schematic, Fig. 2(b)). However, here the more stringent condition s > d √ 2 tan ϕ applies to avoid deposition or milling of the junction area when forming the patch layer. Additionally, it is required that f < s/( √ 2 tan ϕ) to avoid Al deposition on the fringes during deposition of the electrodes, assuming a fringe angle of 45 • (3D schematic on Fig. 2(d)). For all of these inequalities, ϕ is left variable. In our implementation, s = 0.95 µm, f = 0.4 µm, and ϕ = 45 • .
We note that other patch patterns exist, which can connect the junction electrodes to the rest of the circuitthe key is to shape them such that they are shadowed and protected from the evaporating metal when the junction is being made.

COHERENCE CHARACTERIZATION
In order to quantitatively investigate the quality of the junctions made by the new process, we fabricated Xmon qubits and compared their performance against our benchmark. 28 Our study involves two chips designated as S (standard) and P (PICT), each containing three Xmons denoted X1, X2, and X3. To establish a fair comparison between the two processes, we fabricated both chips on the same wafer, so that they would undergo the exact same steps for the ground plane and wiring layer until the wafer was split in two for the fabrication of the junctions and the patches. Each chip was packaged and wire bonded in a copper box, mounted onto the mixing chamber of a dilution refrigerator, and measured at a temperature below 12 mK. Table I presents the qubit parameters. We find that the frequency of each qubit on the P chip matches that of its pair on the S chip within a few tens of MHz, which indicates that the new process did not cause any large variations in the frequency. We measured T 1 and T * 2 for each of the six qubits more than 250 times over a time span of approximately 15 hours in order to capture the statistics of the ubiquitous parameter fluctuations. 28   qubits S-X1 and P-X1, showing very similar values between the chips. For all the qubits, the values of T 1 and T * 2 and their standard deviations are summarized in Table I. Since these qubits have different frequencies, we can most fairly compare their performance by rescaling their T 1 to the quality factor, Q = 2πf 01 T 1 . The average Q for the PICT-JJ qubits is 1.6 × 10 6 , while for the standard qubits, we obtain a negligibly different number: 1.4 × 10 6 .

REPRODUCIBILITY OF JUNCTION RESISTANCE
The transmon qubit is essentially an anharmonic oscillator with fundamental transition frequency 12 Here, the charging energy, In turn, I c is related to the junction normal-state resistance, R N , via the Ambegaokar-Baratoff relation, 29 I c R N = π∆/(2e). These equations indicate that C and R N are the parameters that can influence the reproducibility of the qubit frequency across a wafer. The material and thickness-dependent gap parameter, ∆, is not expected to fluctuate across a wafer at zero temperature. [31][32][33] The capacitance C is dominated by a large planar capacitor with small fabrication-induced variation. Simulation shows that even 0.3 µm variation in the line-width of the capacitor changes the capacitance by ∼1%. As a result, R N is the dominant parameter that causes variation in the qubit frequency, and following the analysis of ref. 6, the deviation in f 01 is half that of R N . Statistical studies of normal resistance have been reported for both niobium-and aluminum-based JJs fabricated using different methods. Bumble et al. 5 found a 2-4% on-chip resistance variation for circular Nb junctions (with AlO x tunnel barrier) of 0.33 µm 2 area. Tolpygo et al. 8 found a value as small as 0.8% for larger-area junctions (1.8 µm 2 ), and 8% for 0.03-µm 2 junctions. Lotkhov et al. 4 reported 10-20% on-wafer spread for Al JJs with junction areas between 0.125 and 0.25 µm 2 . Pop et al. 7 showed 3.5% variation on a single chip for Al JJs with junction areas ranging between 0.02 and 0.2 µm 2 . More recently, a larger-scale reproducibility study over several wafers by Kreikebaum et al. 10 showed an average on-chip variation of 1.8% and a wafer-scale spread of less than 3.5%, although during subsequent fabrication of qubits, it increased to 6.9%.
Using the PICT process, we fabricated thousands of test junctions and measured their resistance for a waferscale study of reproducibility. The 76-mm wafer included forty chips of size 0.5 × 0.5 cm 2 , and each chip had 100 test junctions with 10 different sizes. The focus of this study was on small JJs (0.01 to 0.16 µm 2 ), the typical sizes used for transmon qubits. We measured the junction resistances using an automated probe station at room temperature (only measurements with coefficient of determination higher than 0.99 were considered). Figure 4(a) shows a heat map of the fabrication yield of each chip. The total wafer-scale yield is about 99.1%. The bottom panel of Fig. 4(b) shows the yield as a function of junction size over the whole wafer.
The top panel of Fig. 4(b) shows the mean resistance for each junction size across the wafer, R N (A), on a log scale with error bars representing one standard deviation. The continuous line is a linear fit with a slope of ∼-0.9, close to the expected number of −1, since R N ∝ 1/A. The deviation from the −1 slope is caused by the constant line-width bias (here ∼ 28 nm) in the EBL pattern compared to the CAD design. A heat map for the average normalized resistance, R 0 , of each chip is shown in Fig. 4(c). To obtain R 0 for one junction, its resistance is divided by the mean resistance of junctions with the same size across the wafer, such that R 0 = R N /R N . The observed gradient of R 0 over the wafer may be caused by uneven development and descumming (oxygen plasma). The inter-chip variation of the resistance is 3.7% across the wafer, with a best on-chip number of 1.4% and an average of 2.7%. The variation of R N has a strong size dependence, 8 especially for small junctions, as shown in Fig. 4(d). The figure compares histograms of R 0 for four different junction areas across the wafer. Figure 4(e) shows, in red squares, the coefficient of variation (CV), the standard deviation of R N divided by the mean, as a function of the junction area for all junction sizes.
Variation in R N can be caused by both the tunnel barrier thickness and the junction area A, since where R J is the resistance per unit area of the junction. Assuming R J and A are two independent variables, the CV of R N can be expressed as 34,35 In this equation, CV R J is solely determined by the uniformity of the oxide barrier. On the other hand, to extract the dependence of CV R N on A, we can derive an expression for CV A in terms of A itself. Given the simple case of a square junction with side length d, A = d 2 and σ A = 2dσ d , where σ denotes the standard deviation. Dividing the latter equation by A, we obtain A. Now, σ d is mainly determined by the lithography process, including exposure, development and descumming, and it is assumed to be a certain constant that does not scale with d. One can then fit the data in Fig. 4(e) to equation (3) after substituting for CV A , and extract the constants CV R J and σ d from the fit. We find CV R J = 2.3% and σ d = 3 nm. CV A as a function of the junction area is plotted in Fig. 4(f). This determination of CV A and σ d was done using the nominal, designed junction area; however, we can improve the accuracy by taking into account the previously determined 28 nm line-width bias. In this way, we find CV R J = 1.8% and σ d = 4 nm. For the typical JJ sizes (0.02-0.06 µm 2 ) used for fixed-frequency transmon qubits, σ d = 4 nm corresponds to CV A of 2.9-4.6%. In this case, 60-70% of the total variation in R N is attributed to fluctuations in the junction area, while the rest is attributed to the inhomogeneity of the tunnel barrier.
Improving the reproducibility of R N requires minimizing the two parameters CV R J and σ d . For CV R J , it was shown that the uniformity of the AlO x barrier heavily relies on the uniformity and the morphology of the underlying Al layer, in addition to the oxidation conditions. 36 For σ d , the lithographic process is the main contributor. A high-resolution resist and an optimized EBL process, in addition to an improved recipe of resist development and descumming, can lead to a minimal deviation in the feature size. 10,37 To summarize, we proposed and demonstrated a simplified process to fabricate a Josephson junction and its patch layer that provides a superconducting, galvanic connection of the junction to the circuit. The process relies on shadow evaporation from three angles and fabricates the junction and the patch in only one lithography step. Suitable for making superconducting qubits, our method reduces the total number of junction fabri-cation steps by half without introducing further losses. Moreover, we statistically studied the reproducibility of the junctions and achieved a high fabrication yield. The junctions' resistance variation showed a strong dependence on the width, with an average variation of less than 3.7%, comparable to the best values that are reported by other research groups. The variation can be reduced by optimizing the lithography process, and by improving the uniformity of the tunnel barrier.