Identification of two trapping mechanisms responsible of the threshold voltage variation in SiO$_2$/4H-SiC MOSFETs

A non-relaxing method based on cyclic gate bias stress is used to probe the interface or near-interface traps in the SiO$_2$/4H-SiC system over the whole 4H-SiC band gap. The temperature dependent instability of the threshold voltage in lateral MOSFETs is investigated and two separated trapping mechanisms were found. One mechanism is nearly temperature independent and it is correlated to the presence of near interface oxide traps that are trapped via tunneling from the semiconductor. The second mechanism, having an activation energy of 0.1 eV, has been correlated to the presence of intrinsic defects at the SiO$_2$/4H-SiC interface.

4H-SiC devices technology is still affected by some reliability concerns [1]. As an example, the SiC community is focused on the comprehension of the threshold voltage (Vth) instability phenomena, often observed in 4H-SiC MOSFETs [2,3]. Such Vth instability effects are likely due to electrons tunneling into and out of near-interfacial oxide traps (NIOTs) that extend spatially into the gate oxide from the SiC interface [4,5]. Usually, the SiO2/4H-SiC interface physics is studied on simple MOS capacitors [6,7,8], but the full picture on the real impact of the trapping states can be achieved only studying the real MOSFET device [9].
In this context, we have recently studied the discharge of the NIOTs in later MOSFETs by transient gate-capacitance [5] and gate-current [10,11] measurements. However, the separation of each trapping contribution is fundamental for the comprehension of the SiO2/4H-SiC interface physics. In particular, non-relaxing methods are needed in order to minimize the amount of traps undetected during the investigation. Hence, the role of the SiO2/4H-SiC interface physics is the key factor to control undesired effects of the Vth instability in power MOSFETs. In particular, Sometani et al. [12] have presented a non-relaxation method that allows to measure the Vth using a fixed VG and adjusting the drain-source bias (VDS) value keeping constant the ID. Hence, they have found that the trapped charges with a small detrapping time constant can only be observed in the non-relaxation method. In this context, it results clear that methods that minimize the trap relaxation are needed to access at the intimate mechanisms involved in the threshold voltage instability, i.e. reducing the time between the stress and the measurements and avoiding voltage swings that can hide the stress effect.
Firstly, it is important to understand how to define the threshold voltage (Vth). The standard procedure to determine Vth is the linear fit of the ID 0.5 vs VG. However, this method requires the sweep of the gate bias VG and is essentially insensitive to charge state variation in the gate insulator during the measurement. Since the oxide traps that are very close to the interface will change their charge state not only during the stress but also during the measurement, it is important to monitor the Vth variation keeping constant the applied gate bias in order to quantify also the amount of charge trapped in the oxide during the device qualification process. Hence, it is important to minimize the system perturbation due to the Vth measurement.
In this work, we propose a non-relaxing method based on cyclic gate bias stress that allows to probe the whole 4H-SiC band gap and to separate the contribution of different traps avoiding voltage swings and reducing the time between the stress and the measurement itself. In particular, the drain current at a single gate bias value (ID-VG-read) measurements were used to estimate the variation of the Vth in 4H-SiC lateral MOSFETs after both positive and negative gate bias stress. The interpretation of the experimental results allowed to separate the interface states (Nit) and the near interface oxide traps (NIOTs) to the Vth variation.
Lateral MOSFETs were fabricated on 4°-off-axis n-type (0001) 4H-SiC epitaxial layers (1×10 16 cm -3 ) and an Al-implanted body region (NA~10 17 cm -3 ). The gate oxide was a 40nm thick SiO2 layer [13]. The current voltage (ID-VG) and the drain current transient (ID-t) characteristics of the devices were measured in a CASCADE Microtech probe station, using a Keysight B1505A parameter analyser. Fig. 1 shows the ID 0.5 -VG curves collected in a lateral MOSFET at a fixed drain voltage by increasing the gate bias (VG) up to +30V. The saturation drain current can be described by the following equation [14]: where m is a function of doping density; W is the channel width, L is the channel length, Cox is the gate capacitance and μ is the electron mobility in the channel [14]. It is clear that for large VD values, Eq. 1 can be used to fit the experimental data, and the Vth value can be determined as the intercept with the gate bias axis.
In the presence of Vth instabilities, it is possible to monitor the time dependence of the saturation current ID sat (t). This transient current variation implies that also a threshold voltage variation occurred: The insert in Fig. 1 shows the experimental transient drain current (ID-t) collected at room temperature at fixed VD=+5 V and VG=+20 V on a fresh MOSFET. As can be seen the drain current decreases with the time, thus hinting at an effective variation of the Vth during the measurement. By varying the gate bias stress, the proposed method allows to probe the whole semiconductor band gap and it differs from other methods that require dynamic adjustment of the measurements setup [12] and it is mainly based on simple geometric transformation to extract the Vth. During the cyclic stress procedure, also NIOTs may be stimulated. The NIOTs that are in proximity with the SiO2/4H-SiC interface may be emitted similarly to the interface states resulting undistinguishable. On the other hand, the NIOTs that are located far from the SiO2/4H-SiC interface (up to ~1.3 nm [5]) are slow enough to be measured. In fact, in Fig. 3c it is possible to notice that there is a gap between the starting and the ending point of the circular stress procedure indicating the presence of a residual charge trapped in the NIOTs. Furthermore, as can be noticed in Fig. 4, the total Vth variation occurring in the device decreases increasing the measurement temperature. Fig. 6 shows the estimated amount of Nit and NIOTs from the experimental data depicted in Fig.   4 accordingly with the description illustrated in Fig. 3d. In particular, after the extraction of each value of ΔVth they are converted in terms of the trapped charge according with the following relation: where q is the electron charge, tox and κ are the SiO2 thickness and relative permittivity respectively and ε0 is the vacuum permittivity. Finally, Nit is defined as the ΔVth that occurred from gate bias values of -25 V and + 30 V, while NIOTs is defined as the ΔVth that occurred at VG = 0 V at the end of the cyclic stress (see Fig. 3d). As can be seen, the Nit decreases increasing the temperature (from 6×10 11 cm -2 ) while the NIOTs are nearly constant in the investigated temperature range (about 1×10 11 cm -2 ). The nearly temperature independent NIOTs confirms that charging mechanism is likely due to a tunneling from the semiconductor into the oxide traps and vice versa [5]. On the other hand, the temperature behavior of the Nit can be understood considering a different behavior of the interface states at different temperatures. In particular, considering that during the procedure the Fermi level is to argue that the larger amount of are located interface traps below the conduction band in good agreement with literature data [15,16,17,18]. In particular, it is possible to conclude that -accordingly with Afanas'ev et al. [16] -the Nit with an activation energy of EA=0.1 eV can be associated to the intrinsic interface state defects of the SiO2/4H-SiC system; i.e. oxygen related defects. On the other hand, the estimated NIOTs are most likely defects distributed in the insulator; i.e. residual carbon related defects [5].
In conclusion, a non-relaxing method to probe the threshold voltage instability in 4H-SiC MOSFETs has been used to separate the contribution of two different trapping mechanisms in the SiO2/SiC system probing the whole 4H-SiC band gap. In particular, it has been found than one trapping mechanism is nearly temperature independent and it is most likely related to defect distributed in the insulating layer that are charged and discharged via tunneling. On the other hand, a thermally activated mechanism with an activation energy of 0.1 eV is found to be the most important trapping effect related to intrinsic defects of the SiO2/4H-SiC system.
This work was carried out in the framework of the ECSEL JU project REACTION (first and euRopEAn siC eigTh Inches pilOt liNe), grant agreement no. 783158.