Random telegraph signals caused by a single dopant in a metal oxide semiconductor field effect transistor at low temperature

s of the 2005 International Conference on Solid State Devices and Materials, Kobe, Japan (2005) pp. 864–865. 44S. Sun and J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces,” IEEE Trans. Elec. Dev. 27, 1497–1508 (1980). 45S. Saito, K. Torii, M. Hiratani, and T. Onai, “Analytical quantum mechanical model for accumulation capacitance of MOS structures,” IEEE Elec. Dev. Lett. 23, 348–350 (2002). 46T. Ando, A. B. Fowler, and F. Stern, “Electronic properties of twodimensional systems,” Rev. Mod. Phys. 54, 437 (1982). 47K. Nishiguchi and A. Fujiwara, “Single-electron counting statistics and its circuit application in nanoscale field-effect transistors at room temperature,” Nanotechnology 20, 175201 (2009). 48K. Nishiguchi, Y. Ono, and A. Fujiwara, “Single-electron counting statistics of shot noise in nanowire si metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett. 98, 193502 (2011). 49K. Nishiguchi and A. Fujiwara, “Single-electron stochastic resonance using si nanowire transistors,” Jpn. J. Appl. Phys. 50, 06GF04 (2011). 50C. Beenakker and M. Büttiker, “Suppression of shot noise in metallic diffusive conductors,” Phys. Rev. B 46, 1889 (1992). 51J. B. Johnson, “Thermal agitation of electricity in conductors,” Phys. Rev. 32, 97 (1928). 52H. Nyquist, “Thermal agitation of electric charge in conductors,” Phys. Rev. 32, 110 (1928). 53D. K. Schroder and J. A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” J. Appl. Phys. 94, 1–18 (2003). 54M. Jenei, E. Potanina, R. Zhao, K. Y. Tan, A. Rossi, T. Tanttu, K. W. Chan, V. Sevriuk, M. Möttönen, and A. Dzurak, “Waiting time distributions in a two-level fluctuator coupled to a superconducting charge detector,” Phys. Rev. Research 1, 033163 (2019). 55P. W. Anderson, “Localized magnetic states in metals,” Phys. Rev. 124, 41 (1961). 56M. P. Fisher and A. T. Dorsey, “Dissipative quantum tunneling in a biased double-well system at finite temperatures,” Phys. Rev. Lett. 54, 1609 (1985). 57H. Grabert and U. Weiss, “Quantum tunneling rates for asymmetric doublewell systems with ohmic dissipation,” Phys. Rev. Lett. 54, 1605 (1985). 58K. Ibukuro, J. W. Hillier, F. Liu, M. K. Husain, L. Zuo, I. Tomita, Y. Tsuchiya, H. N. Rutt, and S. Saito, “Dataset for random telegraph signals caused by a single dopant in a metal oxide semiconductor field effect transistor at low temperature,” https://doi.org/10.5258/SOTON/D1193, (University of Southampton, 2020).


I. INTRODUCTION
The importance of atomic-scale features, such as a dopant 1-6 and a trap state [7][8][9][10][11][12][13] has been widely recognised in the context of silicon (Si) quantum technology, such as nanoelectronic circuits 1-4,14-16 information processing [6][7][8][9][17][18][19] , hardware security 12 , bio-sensing 13 and metrology 5,10,11,20,21 . As the size of Si metal-oxide-semiconductor (MOS) fieldeffect-transistors (FETs) approaches to the physical limit, electronic circuits based on single-atom devices were proposed 14,15 . Use of solitary dopants as a fundamental building block of electronic circuits could be a disruptive solution to maintain the rate of device scaling [1][2][3][4]16,22,23 . With regards to quantum information processing, spin qubits based on Si are considered to be promising, due to its weak spin-orbit coupling and abundance of non-magnetic isotopes [17][18][19] . Realising spin-qubits with single-implanted donors are interesting, as they can provide a discrete energy level with larger energy separation due to stronger quantum confinement than the one realised by a quantum dot (QD) defined by patterning or field-effect 6 . Trap states in Si devices have been considered as an impediment to reliable performance of complementary-MOS (CMOS) FETs [24][25][26][27][28][29][30] . However, a few attempts have been made to perform single-spin manipulation based on trap states in a standard MOSFET for spin-qubits, which proved to be successful [7][8][9] . Also, the variation caused by trap states can be used as a fingerprint of a device for hardware security 12 , while a trap state in a liquid-gated FETs for bio-sensing offers enhanced sensitivity to the change in pH of the solution 13 . Finally, such a trap state is known to be useful for a singleelectron pump (SEP) 10,11 for quantum metrology 20,21 . SEP is a periodically driven single-electron transistor with tunable potential barriers, outputting drain current of I d = e f , where a) Electronic mail: ki1m17@soton.ac.uk b) Electronic mail: S.Saito@soton.ac.uk e is the elementary charge and f is the frequency at which the device is driven 20,21 . A SEP that takes advantage of a trap state has achieved 7.4GHz operation with an uncertainty of 20 parts-per-million (ppm) 11 , approaching the metrological requirement of an electric current standard. Without doubt, engineering of such an atomic-scale structures embedded in a Si device will continue to play a crucial part in future quantum applications.
The first challenge in utilising atomic-scale features is to find their signatures in transport characteristics of the devices [31][32][33][34] . We recently proposed characterisation of conventional Si MOSFETs with a long integration time at low temperature, which exhibits Coulomb diamonds (CDs) 31 and random telegraph signals 32 (RTSs) in current-voltage (I-V) characteristics. RTSs are discrete threshold voltage (V th ) variations over time 25,35 , and two V th states are supposed to correspond to an empty and occupied state of a charge trap at Si-SiO 2 interface or inside amorphous SiO 2 32 . The physical origin of the CDs observed in the MOSFETs were, on the other hand, attributed to remote surface roughness of polycrystalline Si (poly-Si) 31 . In this sense, single electron phenomena caused by trap states and structural disturbance in standard MOSFETs have been explored. However, towards application envisaging single-atom circuits [1][2][3][4]16 and spin-qubits 6 , the use of a single dopant is more desirable and suitable.
In order to achieve single-carrier manipulation using a solitary dopant in a conventional MOSFETs, we focused on the dopants in the substrate, and the dopant ionisation profile was electrically tuned in a systematic manner by applying reverse bias to the substrate. By doing this, we observed RTSs caused by a trapping and detrapping of an electron at a donor in the substrate (well) of a p-type Si MOSFET at low temperatures. The device was initially characterised at 3.8K while the substrate was grounded, and it showed a CD in I-V characteristics, indicating that the effective width of the channel is of the order of 10 nm. Also, no RTSs were observed, which means that no trivial charge traps in the oxide or at the interface were present at this bias condition. However, RTSs started to be observed by applying positive bias to the substrate, which can be seen as discrete V th shifts in I-V characteristics. Based on this observation, a physical model to explain this RTS based on trapping and detrapping of an electron at a donor was proposed, where the hole transport was significantly affected by the stochastic change in depletion layer width depending on the charge state of the donor, charge neutral or ionised. The occupancy of the trap level and average lifetimes of two I d states were systematically controlled by gate voltage (V g ), and the dependence of average RTS lifetimes on V g suggests that the physical origin of the RTS could be different from trap states at the interface or in the gate oxide 25,36,37 . The temperature was gradually raised to 25K in order to investigate the dependence of the RTSs on temperature, showing almost no dependence until 16K before the faster RTS switching was observed at higher temperature. This indicates that the trapping and detrapping of an electron is achieved via quantum mechanical tunnelling at low temperature 38 .
This paper also quantitatively discusses the impact of applying reverse bias to the substrate onto the dopant ionisation profile, based on the result of split capacitance-voltage (C-V) measurements with reverse substrate bias 25,39 . Application of substrate voltage have been widely used in the context of Si quantum devices 9,10,40 , though the detailed study on its effect on carrier transport has not been performed. Width of the depletion layer was calculated as a function of V g and voltage applied to the well (V well ), and the depletion layer was constantly extended as V well increased, as expected. Effective hole mobility was also calculated as a function of effective electric field 24,41 , and the degradation of hole mobility was prominent at low effective electric field, where impurity Coulomb scattering is the dominant scattering mechanism. However, regardless of the values of V well , the hole mobility approaches to the universal mobility curve at higher effective electric field, where Si-SiO 2 interface scattering dominates the mobility degradation 24,41 . This confirms that the primary effect of applying reverse bias to the substrate is to widen the depletion layer, rather than to increase the electric field across the MOS structure 24,40 .

II. MOSFET CHARACTERISTIC AT ROOM TEMPERATURE AND LOW TEMPERATURE
A p-type MOSFET fabricated using a standard 65nm technology was characterised at various temperatures (from 300K to 3.8K) with a Janis pulse-tube refrigerator and a Keysight B1500 semiconductor parameter analyser. Figure 1 (a) and (b) show schematics of the cross-sectional and birds-eye views of the device, respectively. The channel length (L) and width (W ) were 50nm and 10µm, respectively, and the capacitive effective thickness (t eff ) is 2.4nm. The device was mounted on and wire-bonded to a cryogenic sample holder, and the p-type handle layer was insulated from the holder by cryogenic varnish. Electrical contact to the n-type region in the substrate, well, was achieved from the dedicated pad connected to the well (Figure 1 (a)). Phosphorous was used to form the well.
From our previous works 31,32 , the presence of a QD was expected in our device, resulting in narrower effective channel width than the actual dimension of the device ( Figure  1(b)). Figure 1(c) show the transfer characteristics (drain current (I d ) against gate voltage (V g )) of the device at both 300K and 3.8K when the drain voltage (V d ) was -50mV and source was grounded (V s = 0mV). At 300K, the subthreshold slope (S = dV g /dlogI d ) was 100mV/decade, while off current (I off ) was around -10pA. As the temperature decreased to 3.8K, S became steeper (14mV/decade) and I off was less than -10fA, which was the expected behaviour of CMOS transistors at low temperatures 24,31 . However, if the channel was considered to be uniform in the subthreshold region at 3.8K, S should have decreased linearly as the temperature decreased, as S = 2.3kT 1 +C dep,m /C ox /e indicates, where k is Boltzmann constant, T is temperature, e is elementary charge, C dep,m is the maximum depletion layer capacitance and C ox is the oxide capacitance 24 . This means that the hole channel is considered to be non-uniform and the dominant current path is much narrower than the actual width of the device. The presence of a QD can be directly verified from 2D contour plots of differential conductance (dI d /dV g ) against V g and V d , shown in Figure 2. I d was measured twice as a function of |V g | (from 0.5V to 0.7V with 1mV increments (forward sweep), and from 0.7V to 0.5V with 1mV decrements (reverse sweep)) with fixed V d to check for the absence of hysteresis, and V d was varied from -30mV to 30mV with 0.2mV increments. Differential conductance was then calculated and the result for the forward sweep is shown in Figure 2. Compliance value of 1µA was set to limit I d , which corresponds to two zero conductance region with |V d | = 30mV and |V g | = -0.7V. Hysteresis was not observed. Several CDs were ob-served, which are highlighted by dotted lines in Figure 2. Two CDs with charging energy of about 5meV (CD1 and CD2) were followed by a sequence of CDs with smaller charging energy (CD3), 1 or 2meV, as |V g | increased. Two CDs with charging energy of 1 or 2meV were also observed at |V g | > 0.65V, which were labelled as CD4 in Figure 2. The presence of CDs, particularly CD1 and CD2, confirms that the dominant transport was through the QD after the transistor turned on. From the charging energy of the dot, the size of the QD can be estimated 14,31 . The charging energy (E c ) is firstly converted to the coupling capacitance of the QD, C Σ by E c = e 2 /C Σ , which gives C Σ = 32aF. C Σ can be decomposed into the coupling capacitance of the QD to source (C S = 15.0aF), drain (C D = 5.42aF) and gate (C G = 11.62aF), from the gradient of the CDs 14,31 . Finally, the size of the QD (S QD ) can be estimated from C G = C eff S QD assuming that the C eff is solely determined by t eff , C eff = ε ox /t eff = 1.44µF/cm 2 . ε ox =3.9ε 0 is permittivity of SiO 2 and ε 0 is permittivity of vacuum, 8.854×10 12 F/m. S QD is 0.808×10 −15 m −2 , and the diameter of the QD (d QD = 4S QD /π) is about 32nm when the shape of the QD is assumed to be rounded 31 . The origin of the QD can possibly be remote surface roughness due to a poly-Si grain in the gate electrode 31,32 . The shrinkage of CDs (CD3 and CD4 are smaller than CD1 and CD2) can be attributed to the change in inversion layer thickness 31 .  These two observations can confirm the transport mechanism in our device at the subthreshold region at low temperature. As |V g | increased and the device began to operate at the subthreshold region, holes would start to flow through a QD first, since it would provide the current path with low potential energy. After |V g | exceeded threshold voltage (V th ), on the other hand, a 2DHG was uniformly formed under the gate dielectric, and the same on current (I on ) of 0.2mA at 300K was achieved (Figure 1(c)). In the subthreshold region located between those two schemes, the carrier transport is thought to be described as a hybrid of the two mechanisms, where holes were predominantly travelling through a narrow, weak link between source and drain involving the QD, resulting in the stan-dard MOSFET characteristic being modulated by Coulomb blockades from the QD (Figure 2), as well as the gentle subthreshold swing (Figure 1(c)).

III. EFFECT OF SUBSTRATE BIAS ON DOPING IONISATION PROFILE
In order to investigate how dopants in the substrate affect the hole transport in the channel, positive substrate bias (V well > 0) was applied such that the dopant ionisation profile would be systematically changed. Application of positive substrate bias means that the p-n junction between source/drain and the substrate was reversely biased, leading to more dopants becoming ionised and therefore fewer mobile holes being introduced from source/drain at a given |V g | to satisfy charge neutrality 24 ; where Q tot is the total charge induced at a certain gate voltage, Q dep is the ionised dopants in the substrate (depletion layer charges), Q inv is the mobile holes introduced from source/drain (inversion layer charges) and ∆Q dep (> 0) and ∆Q inv (> 0) are the increase and decrease in Q dep and Q inv , respectively, due to the reverse bias being applied to the substrate. This effect is called the "body effect" 24 , and |I d | was expected to decrease as V well increased, which is equivalent to a positive |V th | shift 24 .
In order to experimentally obtain Q dep and Q inv as a function of V g and V well , split capacitance-voltage (C-V) measurements with positive substrate bias 42 were performed. From this split C-V measurements, one can quantitatively estimate how many dopants were additionally ionised by the positive V well . This characterisation was performed at room temperature using a Cascade probe station and the B1500. Two devices with (W, L) = (10µm, 10µm) (device B) and (10µm, 4µm) (device C) were measured, which were in the same wafer as the one measured at low temperature (device A), such that the extracted parameters from this measurement can be used for the interpretation of the measurement result obtained from device A. The use of two MOSFETs with different gate lengths is known to be helpful to eliminate parasitic capacitance and resistance 43 . Transfer characteristics with V d = -50mV were obtained prior to the C-V measurements, and the result from Device B was subtracted from the one from Device C to obtain I d . Figure 3 shows drain conductance (g d = I d /V d ) against V g , while V well was varied from 0mV to 500mV with 50mV increments. V g was swept from 1V to -1V with 1mV decrements, and the results were shown from 0V to -1V in linear scale to highlight the shift in |V th |. |V th | was 0.34V when the substrate was unbiased (V well = 0V), and the shift in |V th | towards positive |V g | was clearly observed as V well increased.
Then, in order to characterise capacitance of the devices, AC signal with a frequency of 100kHz and an amplitude of 100mV was applied on top of V g , which was swept from 2V to -1V with 1mV decrements. The out-of-phase current was measured at (1) source and drain together ( Figure  4 (a)) (2) substrate ( Figure 4 (b)) (3) source, drain and substrate altogether, to characterise (1) inversion layer capacitance, C inv = dQ inv /dV g (capacitance due to mobile holes) (2) depletion layer capacitance, C dep = dQ dep /dV g (capacitance due to ionised donors) (3) total capacitance, C tot = dQ tot /dV g (capacitance due to both ionised donors and mobile holes), while (1) V well was applied from 0V to 500mV with 50mV increments (2) V s = V d were applied from 0V to -500mV with -50mV decrements (equivalent to positive V well ) (3) N/A (source, drain and substrate were all used to measure current and substrate bias cannot be applied) in order to see the effect of positive substrate bias on the C-V profile. The capacitance measured from device B in those configurations was subtracted by the capacitance from device C and normalised by the difference in the transistor area between the two devices, 10µm by 6µm. To clarify, C inv , C dep and C tot are given as capacitance per unit area with the unit being µF/cm 2 . From this split C-V measurements, Q inv , Q dep and Q tot are calculated as a function of V g , V well ; where V gs = V g −V s is gate voltage measured from source. Figure 4 shows C inv , C dep at various V well values and C tot against V gs . C inv were plotted by solid lines with a colour gradient from blue (V well = 0mV) to light green (V well = 500mV), while C dep were plotted by solid lines with a colour gradient from red (V s = V d = 0mV, equivalent to V well = 0mV) to purple (V s = V d = -500mV, equivalent to V well = 500mV). Orange empty circles shows C tot against V gs , matching the result of C dep with V well = 0mV in the accumulation region and C inv with V well = 0mV in the inversion region.
C inv shows its dependence on V well in the inversion region (V th > V g ), corresponding to the threshold voltage shift due to the body effect 24 . At a given V g , C inv is lower when positive V well was applied, for example V well = 500mV; Therefore, This result is consistent with the physical picture described in equation (3).
As V well increased, accumulation C-V curves are also shifted towards positive V gs , meaning that flatband voltage (V FB ) is shifted by applying positive V well . This is reasonable, as the flatband condition is determined solely by the difference between V gs and V well − V s , and therefore as V well − V s increased, more V gs needs to be applied in order to achieve the same flatband condition. This parallel V FB shift resulted in the increase in maximum depletion layer charge Q dep,m (Q dep at |V gs | |V th |) by applying positive V well , for example 500mV; which is consistent with equation (2). Table I shows the calculated Q dep,m at various V well values, which proves the inequality (11). So far, from the split C-V measurements, the overall trend expected from body effect (equation (2) and (3)) was experimentally proven. Furthermore, the depletion layer width can be quantitatively obtained as a function of V g and V well . This is equivalent to analyse the ionisation profile of donors in the substrate as V g and V well changes, which gives further insight into the effect of applying V well . To this end, the following model was employed 24 ;  )) describe the measurement setups to characterise C inv and C dep , respectively. C inv against V gs with different V well values (from 0V to 500mV with 50mV increments) are plotted by solid lines with a colour gradient from blue to light green. C dep against V gs with different V well values (from 0V to 500mV with 50mV increments) are plotted by solid lines with a colour gradient from red to purple. Orange empty circles show total capacitance C tot (= C inv +C dep ) at V well = 0V. A simulated C-V curve using analytical quantum mechanical model was plotted in a black broken line.
which is valid when |V gs | > |V FB |. This model means that the total amount of Q dep in the n-well per unit area can be described by the product of the substrate doping (donor) concentration (N d ) and the depletion layer width (W dep ). The spatial variation of N d is ignored in this model and the precise value of N d is not assumed a priori. Firstly, N d is determined from Q dep,m (V well = 0V ) and maximum depletion layer width, W dep,m . After |V gs | exceeds the threshold voltage (|V th |), the depletion layer width is expected to be constant, known as maximum depletion layer width 24 , which is given below; where ε Si = 11.9ε 0 is permittivity of Si and n i is intrinsic carrier density of Si, 10 11 cm −3 . This W dep,m was assumed to be valid only when V well = 0V , and was used as a boundary condition to obtain N d using Q dep,m (V well = 0V ); which gives N d = 5.97×10 17 cm −3 . This means that the average distance between dopant atoms are 12nm, which is in the same scale as the gate length of the device. Using this N d , W dep was calculated as a function of V gs and V well using equation (13), and plotted in Figure 5. W dep against V gs were plotted by solid lines with a colour gradient from red (V well = 0mV) to purple (V well = 500mV). As expected, W dep becomes almost constant after |V gs | exceeds threshold voltage (-0.34V) at any V well . The inset in Figure 5 shows W dep at V gs = -0.5V as a function of V well . This shows that in this model the rate of depletion layer widening upon the application of V well (dW dep /dV well ) is almost constant about 20nm/V. By analysing the change in depletion layer width due to application of V well , it can be concluded that reverse substrate bias can indeed systematically alter the donor ionisation pro-file. The increase in ionised dopants in the substrate does not only reduce the minority carriers in the inversion layer, but also enhance interaction between holes and ionised dopants by remote Coulomb scattering, resulting in the reduction of hole mobility. This can be experimentally confirmed by calculating effective hole mobility (µ 3 )) at various V well values 41 . Solid lines with a colour gradient from blue to light green in Figure 6 show the result, and the black dotted line is the universal mobility curve (µ univ = 185/(1 + E eff 0.45 )) for Si-SiO 2 interface. As can be seen from Figure 6, the degradation of hole mobility is more prominent at low E eff values, where the dominant scattering mechanism is remote Coulomb scattering between holes and ionised donors. At high E eff , however, regardless of V well values, all the mobility curves overlapped and approached to the universal mobility curve. This means that the scattering at the Si-SiO 2 interface, the dominant scattering mechanism at high E eff , has not increased much upon the application of V well , and the enhanced interface scattering does not account much for the degradation of hole mobility. The mobility degradation has been mentioned previously, and the mechanism was considered to be enhanced Si-SiO 2 interface scattering from qualitative discussion 40,44 . Our quantitative result reveals that the enhanced Coulomb scattering is the dominant mechanism to explain the mobility reduction by applying V well .
Mobility degradation due to enhanced Coulomb scattering U n iv e r s a l c u r v e fo r S i -S iO 2 in te r fa c e s c a tt e r in g FIG. 6. Effective mobility (µ eff ) against effective electric field (E eff ) with varied V well at 300K. The degradation of mobility was observed when E eff < 0.5MV/cm with higher V well values, while µ eff -E eff curves approach to the universal mobility curve for Si-SiO 2 interface, indicating that the mobility degradation by applying substrate bias is due to enhanced Coulomb scattering.
The reliability of the C-V measurements was assured from good agreement with the numerical simulation based on analytical quantum mechanical model 45 . This model assumes the potential exponentially depends on the distance from the Si-SiO 2 interface, which allows one to find an exact solution of Schrödinger equation. The solution is then feed-backed into Gauss's law, which determines the parameter of the exponential potential, resulting in self-consistent Poisson-Schrödinger equation 45 . The result of C-V simulation is shown in Figure  4 as a black dashed line, which agreed well with the experimental result with equivalent oxide thickness (EOT) of 2nm being used as a fitting parameter. Other input parameters were N d = 6×10 17 cm −3 and V FB = 1.01V, which were determined from equation (15) and maximum curvature of the C-V curve in accumulation region, respectively. The difference between t eff = 2.4nm and EOT = 2nm is attributed to the quantum confinement near the Si-SiO 2 interface, which can be converted into width of wavefunction in Si, t Si = (t eff − EOT) × ε Si /ε ox = 1.2nm, which is reasonable 31,45,46 .

IV. RANDOM TELEGRAPH SIGNALS TRIGGERED BY REVERSE SUBSTRATE BIAS
After investigating the effect of substrate bias on the dopant ionisation profile in the substrate, detailed I-V scans with positive V well were performed to see its effect on the hole transport in the device. Figure 7 (a) to (f) show 2D contour plots of I d as a function of V g and V d at V well = 0V, 100mV, 200mV, 300mV, 400mV and 500mV. V g and V d were swept from -0.5V to -0.7V and 30mV to -30mV with 1mV and 0.2mV decrements, respectively, and the results within -0.7V < V g < -0.6V and -15mV < V d < 15mV are displayed. Even at current range of sub-µA, the presence of CD4 can be clearly seen. Also, as V well increased, |V th | shifted towards higher |V g |, as expected. Another notable feature in Figure 7 (c) to (e) is that a few discrete current peaks were observed, highlighted by arrows in the figures. Such current peaks were not observed when V well = 0V (Figure 7 (a)) and the number of current peaks seen in Figure 7 (a) and (f) (V well = 100mV and 500mV) is much less than Figure 7 (c), (d) and (e) (V well = 200mV, 300mV and 400mV). This indicates that the peaks could only be observed around a certain V well value. The current peaks were observed for both positive and negative V d , and the ones in negative V d (V d < 0) are addressed in the following discussion. To clarify the nature of the current peaks, I d -V g curves with V well = 200mV and |V d | varying from 7mV to 13mV with 1mV increments are displayed in Figure 8. Forward sweeps (increasing |V g |) are shown with solid lines, while reverse sweep (decreasing |V g |) are shown with dotted lines. Discretised threshold voltage shifts of about 1.5mV were observed around |V g | = 0.65V in Figure 8, which coincides with the current peaks observed in 2D contour plots. The threshold voltage shifts continued to be observed with higher |V d |. The inset of Figure  8 shows I d -V g curve with V well = 200mV and |V d | = 30mV, showing the same threshold voltage shift.
To confirm that the observed threshold voltage shift is caused by a single carrier [47][48][49] , |I d | was monitored over 1000s (time domain characteristic). The interval of measurements was 100ms, and the integration time (included in the interval) was 20ms. Figure 9 (a) to (e) show the time domain characteristic at various |V g | (from large |V g | to small |V g |), while Figure 9 (f) to (j) show corresponding histograms (probability to observe a certain current value) for each time trace. |V d | was fixed at 30mV to increase the signal to noise ratio between the high |V th | state (= the low |I d | state) and the low |V th | state (= the high |I d | state). When |V g | was 0.62V ( Figure  9 (e) and (j)), |I d | was stable around 0.143µA. The random switching between two states started to be observed at |V g | = 0.639V, which can also be identified from the two peaks in the histogram (Figure 9 (j)). The probability of the two states was almost equal at |V g | = 0.645V, and the low current state was the dominant state at |V g | = 0.655V, indicating that the probability to observe one of the states are well controlled by the gate voltage. These |V g | values coincide with the range of |V g | in Figure 8 where the threshold voltage shifts were observed, meaning that the nature of the shifts were RTSs. Also, as the switching was between only two states, the fhysteresis in |I d | observed in Figure 8 was due to trapping and de-trapping of a single carrier and no multiple charge states were involved [47][48][49] . At |V g | = 0.725V, |I d | was stable around 5.02µA and the random switching between two current states were not observed.

V. DISCUSSION; SINGLE ELECTRON TRAPPING AND DE-TRAPPING IN THE SUBSTRATE
In the previous sections, the I-V and C-V characteristics of pMOSFETs at room temperature and low temperature were introduced (Section II, III), before unexpected observation of RTSs at 3.8K by the application of positive substrate voltage (V well ) were shown in detail (Section IV). The biggest difference from conventional RTSs observed in CMOS devices [24][25][26][27][28][29][30] is that the RTSs were only observed when positive bias was 8. I d as a function of V g with V well = 200mV and varied V d of (main) -7mV to -13mV with 1mV decrements and (inset) -30mV at 3.8K. Blue solid lines show the results for forwards sweeps (|V g | increased from 0.62V to 0.66V), while pink broken lines show the results for reverse sweeps (|V g | decreased from 0.66V to 0.62V). It took 72s for |V g | to be swept from 0.62V to 0.66V. applied to the substrate such that the depletion layer was further widened from its maximum width 24,25 . Although the modification of RTSs parameters, such as ∆|I d |, lifetime of the two current state (τ High and τ Low ), by applying V well was previously reported 25,39 , RTSs triggered by applying V well have not been observed so far. As seen in Section III, the primary effect of applying reverse substrate bias is to increase ionised donors in the substrate and widen the depletion layer, which result in a positive |V th | shift. Therefore, we attribute the origin of the RTS to a dopant atom ionised by the application of positive V well , capturing and re-emitting an electron and shifting |V th | accordingly. The presence and absence of a single electron in the substrate and resulting change in the depletion layer width could have a significant impact on the hole transport, as the effective width of the channel was limited by the size of the QD, about 32nm, at low temperature (Figure 1). Figure 10 illustrates the proposed physical model to explain the mechanism of the RTS. When V well was grounded (0V), a dopant atom was below the Fermi energy (E F ) and therefore filled with an electron, meaning that it could not affect the hole transport in the inversion layer (Figure 10 (a)). As V well increased, the depletion layer extended and the dopant level was subsequently raised, resulting in the dopant level aligned with E F (Figure 10 (b) and (c)). At this condition, both situations where the dopant was ionised or filled with an electron were energetically equally favourable, such that the switching between those two charge states would occur. Further increase in V well would result in complete ionisation of the dopant, and the dopant could not influence the transport anymore. In order to justify this model, we estimate how much V well is required to ionise one dopant under the QD, δV well . The extension of depletion layer, δW dep , is defined such that the volume under QD (S QD δW dep ) contains one donor, S QD δW dep N d = 1. This results in δW dep = 2.1nm, and therefore δV well = δW dep (dW dep /dV well ) −1 is about 0.1V, which is of the same orders of magnitude with V well causing the RTSs. Considering the uncertainty associated with the size of the QD, this estimation is in good agreement with our observation.
This claim can also be supported from the direction of |V th | shift due to RTSs. As |V g | increased, the dominant current state shifted from the high |I d | state to the low |I d | state, corresponding to the positive threshold voltage shift (Figure 9). This can be explained by the ionisation of a single dopant due to the increased |V g |. The dopant was initially well below E F , before being brought into E F by applying positive V well . Then, as |V g | increased, the conduction band became bent further and the dopant level became in resonant with E F , resulting in an electron escaping and re-entering the donor level by quantum mechanical tunnelling or thermal activation. This ionisation contributed to the further widening of the depletion layer, leading to the positive |V th | shift, consistent with the observation (Figure 9). Further increase in |V g | would result in complete ionisation of the dopant, and RTSs would not be observed anymore.

VI. TRAPPING AND DETRAPPING PROCESS OF AN ELECTRON
In the previous section, the physical origin of the RTS was suggested to be a dopant in the substrate, and two current states, high |I d | state and low |I d | state, were attributed to be two charge states, charge neutral and ionised, respectively. In order to study the mechanism of the RTS further, the statistics of the signal were investigated in detail 25 . Figure 11 shows the occupancy of each of the two current states, which is the probability to observe the high |I d | state (N High ) or the low |I d | state (N Low ) against gate voltage. N High and N Low were defined as follows 33,34 ; where P(|I d |) is the probability to observe a certain |I d | value (Figure 11), I d = 1 2 (I d,High + I d,Low ) is the average |I d | value of the high |I d | state (I d,High ) and the low |I d | state (I d,Low ), and I T = ∞ −∞ P(|I d |)d|I d | is a normalising factor. As |V g | increased, N High decreased and N Low increased, which is consistent with the transfer characteristic ( Figure 8) as well as time domain measurement and their corresponding histograms (Figure 9). At |V g | = 0.645V, N High and N Low became almost equal, meaning that at this bias condition the high |I d | state and the low |I d | state were energetically almost equally favourable.
Asymmetry was found in N-|V g | characteristic ( Figure 11) around |V g | = 0.645V. RTSs cannot be detected when |V g | was smaller than 0.639V, where the high |I d | state dominates (about up to 80%). However, RTSs were still observed when |V g | were more than 0.66V, where the dominant low |I d | state, exceeded 80%. This asymmetry can be attributed to nonlinear |I d | -|V g | characteristics 34 . Firstly, |I d | is not only susceptible to RTSs, but also disturbed by analogue noise such as shot noise 50 , thermal noise 51,52 , negative bias temperature instabilities (NBTI) 53   amplitude of RTSs (∆|I d |) needs to be larger than the deviation around the mean value of each current state, which can be characterised by full width of half maximum (FWHM) of each current state. If |I d | is a linear function of |V g |, ∆|I d | would be a constant value, and to the extent that the value is larger than FWHMs of both states RTSs should be detected, resulting in a symmetrical N-|V g | characteristic. If |I d | increases faster than a linear function (|V g | 2 for example), ∆|I d | would increase as a function of |V g | 34 , and detecting RTSs would be difficult at small |V g | since FWHM and ∆|I d | are comparable. Figure 11 inset shows FWHM of both the high |I d | state (FWHM High ) and the low |I d | state (FWHM Low ), and ∆|I d | against gate voltage. A double Gaussian function was used to fit the probability against |I d | to obtain FWHM High , FWHM Low and ∆|I d |. While ∆|I d | and FWHM High , FWHM Low were comparable at |V g | = 0.639V, as |V g | increased ∆|I d | exceeded both FWHM High , FWHM Low , making it easy to distinguish two current states. Increasing the integration time may be useful to average out the fluctuation around the mean value of each current state. The characteristic of RTS lifetimes (τ High , time-to-emission and τ Low , time-to-capture, defined in this paper), particularly its dependence on V g , is considered to reflect the physical origin of the signal 36,37,39 . If the origin of the RTS is a trap in the oxide, the way the average lifetimes ( τ High and τ Low ) depend on V g is considered to be asymmetric 36,37,39 . This is because the probability for a carrier to be captured by a trap depends both on the carrier density in the inversion layer and V g . V g determines the energy level of a trap with respect to Fermi energy, and as V g increases the trap level would become lower and it would be predominantly occupied. In addition, if the carrier density is higher, the chance of a carrier to be captured by a trap would increase further. The emission process, on the other hand, only depends on V g as there is no other electron to be emitted. This difference in capture and emission process causes the difference in behaviour of time-to-capture and time-to-emission against V g , where timeto-capture strongly depends on V g while time-to-emission is almost a constant 36,37,39 . Our model is based on a dopant exchanging an electron with n-doped well with fixed density of N d , suggesting that both τ High and τ Low should be modified by |V g |. Therefore, by calculating τ High and τ Low as a function of V g , the observed RTS can be distinguished from the one caused by a trap in the oxide.
As far as the average values of τ High and τ Low ( τ High and τ Low ) are concerned, they can be efficiently obtained from the histogram of time differential of |I d | (δ I d (t) = |I d (t + ∆t)| − |I d (t)|), P(δ I d ) 33 ; where T High = N High T , T Low = N Low T , N total is the total number of measurement points during T and δ I T = ∞ −∞ P(δ I d )dδ I d is a normalisation factor. The denominator FIG. 11. Occupancy of the two current states (N High and N Low ) against V g . N High and N Low at 3.8K were plotted with solid blue square and filled magenta circles, while those at 12K were plotted with triangles with orange lines and diamonds with green lines, respectively. (Inset) Full width of half maximums of the two current states (FWHM High and FWHM Low ) and the amplitude of the random telegraph signals (∆|I d |) against V g at 3.8K.
in equation (18) ( (19)) is the number of transitions from high (low) |I d | state to low (high) |I d | state. Figure 12 (a) displays τ High and τ Low against |V g |. Similar to the N-|V g | characteristic, two curves ( τ High -|V g | and τ Low -|V g |) were crossing at |V g | = 0.645V. While the dependence on |V g | is different, both τ High and τ Low were modified by |V g |, meaning that the result suggests that the physical origin of the RTS could be a dopant and also different from a trap in the oxide. Further advanced measurement, such as single-electron spin resonance 8 can be a next logical step, which is however out of the scope of this paper. Figure 12 (b) and (c) are the probability distribution of individual transitions (from the high |I d | state to the low |I d | state and from the low |I d | state to the high |I d | state, respectively) when |V g | was fixed to 0.645V. For this particular measurement I d was monitored for 10000s with ∆t being 1s so that the longer time trace could be taken without increasing the data points while ∆t was short enough to capture the RTS with average lifetimes of 20s. The distributions can both be well approximated by an exponential curve, indicating that there was no periodicity in this signal and also the finite detection bandwidth of the measurement did not affect the statistics of the observed RTS 54 .
From the analysis on τ High and τ Low as a function of V g , a dopant in the substrate is considered to be a realistic candidate of the physical origin of the observed RTS. In order to further validate this physical model, finally the device was measured at temperatures up to 25K. RTSs were observed at a similar |V g | range at higher temperatures as well. The rise in the temperature certainly shifted the threshold voltage, though the statistics of RTS has not been significantly changed, as can be seen from Figure 11. N-|V g | characteristics at 12K are shown in Figure 11, and similar to the case of 3.8K, N High -|V g | and N Low -|V g | curves cross at |V g | = 0.645V, meaning that both states were observed equally frequently at 12K as well. Then, time domain measurements were taken at |V g | = 0.645V and different temperatures (5, 7, 10, 11, 12.5, 14, 16, 20 and 25K). Figure 13 shows the average lifetimes of the high and low |I d | state against inverse of temperature T (1000/T ), while |V g | was fixed to 0.645V. This graph indicates that the lifetimes were temperature independent up to 16K, and became faster as the temperature rose to 20 and 25K. This trend can be understood in a way that the mechanism of the trapping and detrapping of an electron transit from quantum mechanical tunnelling at low temperature to thermal activation at higher temperatures 38 ; where P quantum and P thermal are probability for an electron to become trapped or detrapped via quantum mechanical tun-  13. τ High and τ Low against the inverse of the temperature, 1000/T, at |V g | = 0.645V . τ High are plotted with solid blue squares, while τ Low are plotted with magenta empty circles. The orange dotted line is an Arrhenius plot with an activation energy of 26meV, while the broken green line is the average value of the lifetimes at lower temperature (from 3.8K to 14K). The inset describes the two mechanisms of trapping and detrapping of an electron, quantum mechanical tunnelling and thermal activation, in an energy band diagram.
nelling and thermal activation per 1s, τ q is an attempt interval for the quantum mechanical tunnelling to occur, ∆E is the activation energy for the thermal activation process to occur, τ th is an attempt interval for the thermal activation provided the activation energy is negligibly small, τ experiment is experimental data, such as τ High and τ Low . This model means that the total probability of trapping and detrapping of an electron can be described by the sum of the probability of such a carrier exchange to occur via quantum mechanical tunnelling and thermal activation. The inset of Figure 13 describe two mechanisms in an energy band diagram. The orange arrow represents thermal activation, where an electron escapes from a dopant with thermal activation, similar to how free carriers are provided in the conduction band of bulk Si. The green arrow describes the quantum mechanical tunnelling, where an electron tunnel through the potential barrier between a dopant and highly doped region. We used this model to qualitatively explain the temperature dependence of the average lifetimes. The orange dotted line in Figure 13 is an Arrhenius plot with ∆E of 26meV, requirement for a dopant to provide carriers at room temperature, and the green broken line shows the average value of the lifetimes at the temperatures from 3.8K to 14K, 18.04s. These two lines can approximately reproduce the trend observed in Figure 13. This result indicates that the coupling of a single dopant to the electron reservoir (well) at 3.8K is quantum mechanical, indicating that the system in our device can be described by the renowned single impurity Anderson model 55 . Quantum tunnelling rates can also be associated with the analytic solutions in the case of biased doublewell systems 56,57 .

VII. CONCLUSION
In this paper, observation of random telegraph signals caused by a single dopant in the substrate of a ptype metal-oxide-semiconductor field-effect-transistor was reported. RTSs were initially not observed until the substrate bias was applied such that the depletion layer becomes widened. Trapping and detrapping of an electron changed the depletion layer width under the narrow channel involving a quantum dot, which worked as a sensitive charge sensor. Statistics of individual lifetime of the RTSs obeyed the exponential distribution, and the occupancy of the two current states as well as lifetime were controlled by the gate voltage, as expected. Average lifetimes associated with the discrete current states were modified by gate voltage significantly, indicating that the origin of the signal differs from trap states in the oxide. The temperature dependence of the average lifetime indicates that the tunnelling mechanism transited from quantum mechanical tunnelling to thermal activation as the temperature increased. Engineering of an atomic-scale features and manipulation of a single carrier are crucially important for quantum technology for nanoelectronics 1-4,14-16 , metrology 5,10,11,20,21 and even for quantum information processing [6][7][8][9][17][18][19] . We focused on a dopant in the substrate, and realised single-electron manipulations in an industry-grade Si MOSFET in a reasonably easy manner at a relatively higher temperature of 3.8K. Our work proposes an alternative approach to utilise the existing yet to date little considered candidate of such an atomic-scale feature, a solitary dopant in the substrate, for future quantum application.

DATA AVAILABILITY STATEMENT
The data that supports the findings of this study are openly available in ePrints Soton, the University of Southampton Institutional Research Repository (https://doi.org/10.5258/SOTON/D1193) 58 .