Hybrid integration of carbon nanotube and amorphous IGZO thin-film transistors

Solution-processed carbon nanotubes (CNTs) have recently attracted significant attention as p-type thin-film transistor (TFT) channels due to their high carrier mobility, high uniformity, and low process temperature. However, implementing sophisticated macroelectronics with a combination of single CNT-TFTs has been challenging because it is difficult to fabricate n-type CNT-TFTs. Therefore, in combination with indium-gallium-zinc-oxide (IGZO), which has excellent electrical performance and has been commercialized as an n-type oxide TFT, we demonstrated various hybrid complementary metal-oxide semiconductor integrated circuits, such as inverters and NOR and NAND gates. This hybrid integration approach allows us to combine the strength of p-type CNTand n-type IGZO-TFTs, thus offering a significant improvement for macroelectronic applications. © 2020 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). https://doi.org/10.1063/1.5139085., s High-performance flexible electronics are highly desirable for wearable, medical, healthcare, and robotics applications. Carbon nanotubes (CNTs) are promising candidates for high-performance flexible electronics due to their high carrier mobility, high current density, high mechanical flexibility/stretchability, and compatibility with printing processes. In particular, highly purified semiconducting CNTs have attracted widespread attention for manufacturing diodes, field-effect transistors (FETs), thin-film transistors (TFTs), and integrated circuit (IC) applications. In addition, TFTs with record-breaking performance have been reported using CNTs achieved from a density-gradient ultracentrifugation method, with semiconducting purity above 99%. However, CNTTFTs typically exhibit p-type properties under ambient conditions due to the adsorption of oxygen and water vapor; therefore, if the ICs are implemented with only CNTs, they are expected to exhibit poor electrical performance. There have been many efforts to convert p-type operations to n-type operations, but controllability and stability issues remain difficult to resolve. To overcome the aforementioned issues, new concepts of CNT-based IC applications, such as pseudocomplementary metal-oxide semiconductor (CMOS) combination circuits and diode-based circuits, have been demonstrated. Nevertheless, complex process steps, low integration, and high manufacturing costs remain. Recently, as interest in macroelectronic circuits with low static power consumption has increased, hybrid combinations of complementary materials such as CNTs and amorphous indiumgallium-zinc-oxide (IGZO) have widely been studied for various complementary circuits. IGZO is one of the most promising members in the amorphous oxide semiconductor category, with excellent n-type electrical performance. In particular, IGZObased TFTs have been successfully employed in pixel driving circuits, such as liquid crystal displays (LCDs) and organic light emitting diodes (OLEDs), for commercial display applications. Here, we demonstrate a hybrid integration based on p-type CNT-TFTs and n-type IGZO-TFTs to achieve hybrid CMOS ICs, which are a potential candidate to replace silicon CMOS technology. We evaluated the electrical performances of devices (CNTand IGZO-TFTs) and ICs (inverters and NAND and NOR gates). The fabricated CNTand IGZO-TFTs showed high on-state current (ION), high on/off current ratio [log(ION/IOFF)], and high carrier AIP Advances 10, 025131 (2020); doi: 10.1063/1.5139085 10, 025131-1

High-performance flexible electronics are highly desirable for wearable, medical, healthcare, and robotics applications. [1][2][3] Carbon nanotubes (CNTs) are promising candidates for high-performance flexible electronics due to their high carrier mobility, high current density, high mechanical flexibility/stretchability, and compatibility with printing processes. [4][5][6][7][8] In particular, highly purified semiconducting CNTs have attracted widespread attention for manufacturing diodes, field-effect transistors (FETs), thin-film transistors (TFTs), and integrated circuit (IC) applications. [9][10][11][12] In addition, TFTs with record-breaking performance have been reported using CNTs achieved from a density-gradient ultracentrifugation method, with semiconducting purity above 99%. 13 However, CNT-TFTs typically exhibit p-type properties under ambient conditions due to the adsorption of oxygen and water vapor; [14][15][16] therefore, if the ICs are implemented with only CNTs, they are expected to exhibit poor electrical performance. There have been many efforts to convert p-type operations to n-type operations, [17][18][19][20] but controllability and stability issues remain difficult to resolve. To overcome the aforementioned issues, new concepts of CNT-based IC applications, such as pseudocomplementary metal-oxide semiconductor (CMOS) combination circuits and diode-based circuits, have been demonstrated. 21,22 Nevertheless, complex process steps, low integration, and high manufacturing costs remain.
Recently, as interest in macroelectronic circuits with low static power consumption has increased, hybrid combinations of complementary materials such as CNTs and amorphous indiumgallium-zinc-oxide (IGZO) have widely been studied for various complementary circuits. 16,[23][24][25] IGZO is one of the most promising members in the amorphous oxide semiconductor category, with excellent n-type electrical performance. 26,27 In particular, IGZObased TFTs have been successfully employed in pixel driving circuits, such as liquid crystal displays (LCDs) and organic light emitting diodes (OLEDs), for commercial display applications. 28 Here, we demonstrate a hybrid integration based on p-type CNT-TFTs and n-type IGZO-TFTs to achieve hybrid CMOS ICs, which are a potential candidate to replace silicon CMOS technology. We evaluated the electrical performances of devices (CNTand IGZO-TFTs) and ICs (inverters and NAND and NOR gates). The fabricated CNT-and IGZO-TFTs showed high on-state current (ION), high on/off current ratio [log(ION/IOFF)], and high carrier ARTICLE scitation.org/journal/adv mobility (μFE). By employing these TFTs, the hybrid CMOS inverters exhibited excellent electrical performances with low power consumption and high voltage gains. Finally, we also demonstrate the operations of the two-input NAND and NOR gates fabricated based on the CNT-and IGZO-TFTs. As a result, the logic circuits provide correct logical functions according to input signals. We believe that the hybrid integration approach combines the strength of ptype CNT-and n-type IGZO-TFTs for high-performance CMOS IC designs. Figure 1(a) illustrates the details of the fabrication processes of a hybrid CMOS inverter based on the CNT-and the IGZO-TFTs, and the two-input NAND and NOR gates also have the same process steps. First, the hybrid device fabrication was initiated on a silicon (Si) wafer with a thermally grown 300-nm-thick silicon dioxide (SiO 2 ) layer. Next, the titanium (Ti) local bottom gate with a thickness of 20 nm was deposited with an electron-beam (e-beam) evaporator. An aluminum oxide (Al 2 O 3 ) with a thickness of 40 nm was grown as a gate insulator through atomic layer deposition (ALD) at 80 ○ C, and then, a 10-nm-thick SiO 2 layer was formed using e-beam evaporation for effective semiconducting CNT network formation. At present, the formation of the bottom gate and gate insulator is the same process for p-type CNT-and n-type IGZO-TFTs. To fabricate the p-type CNT-TFT, the surface of the SiO 2 layer was first cleaned by oxygen plasma treatment for 1 min at 30 W. The substrate was functionalized with a poly-L-lysine solution (0.1% w/v in water; Sigma Aldrich) by dropping the solution onto the SiO 2 surface to introduce an amine-terminated adhesion layer for the efficient deposition of the CNT percolated network, 29,30 followed by rinsing with de-ionized (DI) water. Subsequently, to deposit the semiconducting CNT network, the substrate was immersed into a commercially available 0.01 mg/ml 99% semiconducting CNT solution (purchased from NanoIntegris, Inc.) for 20 min with elevated temperature at 100 ○ C and was thoroughly rinsed with DI water and isopropanol. Afterward, the p-type CNT source and drain (S/D) electrodes consisting of Ti and palladium (Pd) layers (each 2 nm and 30 nm, respectively) were formed using e-beam evaporation and a lift-off process. Next, to define the percolated CNT network channel, additional photolithography and an oxygen plasma-etching process were conducted to remove unwanted electrical paths, which isolated the devices from one another. Thus, the fabrication of the p-type CNT-TFTs is completed.
Subsequently, to form n-type IGZO-TFTs, the 35-nm-thick IGZO film (In:Ga:Zn = 1:1:1 at. %) was deposited by radio frequency (RF) sputtering at 150 W in an argon and oxygen (Ar/O 2 ) mixture (3:0.1 sccm) at room temperature and patterned by a lift-off process. Then, Ti and gold (Au) layers (each 20 nm and 20 nm, respectively) were deposited using an e-beam evaporator to serve as the S/D electrodes, followed by a lift-off process. To open the gate contact pad, a photolithography process was performed, and the gate insulator (Al 2 O 3 /SiO 2 ) was wet-etched in a diluted hydrofluoric acid (HF) solution for 40 s. Next, 200-nm-thick SiO 2 was deposited by plasma enhanced chemical vapor deposition (PECVD) as an interlayer dielectric (ILD) layer, followed by wet etching in a diluted HF solution to open the S/D contact pads. Finally, Ti and Au layers (each 5 nm and 200 nm, respectively) were deposited with an e-beam evaporator as the metallization process for device-to-device interconnections; thus, hybrid CMOS ICs were completed.  Figure 1(b) depicts the optical microscope image of the hybrid CMOS inverter. Atomic force microscopy (AFM) images of the 99% semiconducting CNT network and the IGZO thin film are shown in the channels of p-type and n-type TFTs, respectively. From the AFM images, it is confirmed that the CNT network channel and IGZO thin-film were uniformly formed across the entire area. The average CNT density obtained for 20 min deposition was extracted as 75 tubes/μm 2 ± 4 tubes/μm 2 , and the surface roughness of the IGZO thin-film was 0.3 nm.
The defined channel lengths (L) and widths (W) in the fabricated CNT-and IGZO-TFTs ranged from 2 μm to 50 μm and from 2 μm to 50 μm, respectively. Figure 2(a) exhibits the transfer characteristics (i.e., drain current, −IDS, vs gate voltage, VGS) of the p-type CNT-TFTs with a W of 10 μm and an L of 5 μm at a drain voltage (VDS) of −0.5 V. The measured CNT-TFTs appear to operate with good p-type behavior. The key metrics of the CNT-TFTs, such as normalized ION, i.e., −ION × L/W (ION of the CNT-TFTs is defined at VGS = −5 V and VDS = −0.5 V), log(ION/IOFF) (the off-state current, IOFF, is defined at VGS = 3 V and VDS = −0.5 V), and μFE, were determined to be 3.31 μA ± 0.75 μA, 4.72 cm 2 /V s ± 0.28 cm 2 /V s, and 45.2 cm 2 /V s ± 7.4 cm 2 /V s, respectively. The μFE of CNT-TFTs was determined using the current-voltage equation and by calculating a sophisticated cylindrical model. 31 The representative output characteristics (i.e., −IDS vs VDS) of the CNT-TFTs at various VGS values are shown in Fig. 2(b). Furthermore, semiconducting CNT-TFTs present clear IDS saturation behavior, as shown in the output characteristics. Importantly, these curves appear to be linear at small VDS values, indicating that ohmic contact is well formed between the Pd S/D and the CNT networks. In addition, Figs. 2(c) and 2(d) show the transfer and output characteristics of the n-type IGZO-TFTs with a W of 50 μm and an L of 5 μm at a VDS of 0.5 V. The typical ION × L/W defined at VGS = 5 V, the log(ION/IOFF) (IOFF of the IGZO-TFTs is defined at VGS = −3 V), and μFE were extracted as 3.24 μA ± 0.91 μA, 5.95 cm 2 /V s ± 0.85 cm 2 /V s, and 23.3 cm 2 /V s ± 4.5 cm 2 /V s, respectively. We confirmed the good saturation behavior of the IGZO-TFTs, with ohmic contacts between the Ti/Au S/D and the IGZO thin-film as well. As a result, as shown in the output characteristics, the electrical performance of the CNT-and the IGZO-TFTs is not symmetrical; hence, the device geometry of the CNT-TFT with W/L = 10/5 μm and that of the IGZO-TFT with W/L = 50/5 μm were chosen as the optimized conditions used in the hybrid CMOS ICs. Figure 3(a) shows a schematic diagram of a hybrid CMOS inverter based on p-type CNT-and n-type IGZO-TFTs. Figure 3 These results show higher voltage gains at lower VDD than the previously reported hybrid CMOS inverters based on CNT-and IGZO-TFTs 23,24 due to our optimized process conditions. By controlling the device dimensions and process conditions, we were able to achieve the enhanced performances, regarding log(ION/IOFF), μFE, and ION, which also

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scitation.org/journal/adv  16 In addition, the maximum power consumption of the fabricated hybrid CMOS inverter is 9.8 μW at a VDD of 10 V, which indicates low power consumption of our hybrid CMOS inverter. The key metrics of the mentioned CNT-and IGZO-TFTs and hybrid CMOS inverter composed of them are quantitatively summarized in Table I. Figure 4(a) presents a schematic illustration of a two-input hybrid NOR gate implemented based on p-type CNT-and n-type IGZO-TFTs. The NOR gate is realized by connecting two CNT-TFTs in series and two IGZO-TFTs in parallel. The NOR gate demonstrates a rail-to-rail voltage swing from 0 V to 10 V at a VDD of 10 V. Figure 4(b) shows the output of the NOR gate that correctly returns the output of logic "1" state (10 V) only at the condition when both of the inputs (VA and VB) are set to logic "0" state (0 V) or when both IGZO-TFTs are turned off. Figure 4(c) shows a schematic circuit diagram of the NAND gates, which are achieved by connecting two CNT-TFTs in parallel and two IGZO-TFTs in series. Figure 4(d) also illustrates the output of the NAND gate returning correctly a signal logic "0" state (0 V) only when both of the inputs are logic "1" state (10 V) or when both CNT-TFTs are turned off. Logic circuits such as NAND and NOR gates return accurate output signals based on their input logics, which are some of the basics in modern digital IC. This allows the design of hybrid CMOS ICs to further explore the possibilities of implementing high-performance digital logic circuits.
In conclusion, we demonstrated a hybrid integration based on p-type CNT-and n-type IGZO-TFTs to implement hybrid CMOS ICs. Individual CNT-and IGZO-TFTs with high ION, high log(ION/IOFF), and high μFE were fabricated, and the two TFTs exhibited balanced electrical performance. Furthermore, by employing these TFTs, we implemented a hybrid CMOS inverter with high voltage gain and low power consumption. We also show the operations of the two-input NOR and NAND logic gates fabricated with a combination of CNT-and IGZO-TFTs. As a result, the NOR and NAND gates return correct logical functions according to input signals. We believe that our approach of hybrid integration of CNT-and IGZO-TFTs offers great improvement for various macroelectronic applications.