Free-standing silicon shadow masks for transmon qubit fabrication

Nanofabrication techniques for superconducting qubits rely on resist-based masks patterned by electron-beam or optical lithography. We have developed an alternative nanofabrication technique based on free-standing silicon shadow masks fabricated from silicon-on-insulator wafers. These silicon shadow masks not only eliminate organic residues associated with resist-based lithography, but also provide a pathway to better understand and control surface-dielectric losses in superconducting qubits by decoupling mask fabrication from substrate preparation. We have successfully fabricated aluminum 3D transmon superconducting qubits with these shadow masks, and demonstrated energy relaxation times on par with state-of-the-art values.

Progress in superconducting circuits for quantum information technologies relies on the improvement of superconducting qubit lifetimes 1 . One of the main sources of energy loss in these devices comes from the dielectric surfaces surrounding the Josephson junctions and associated superconducting circuitry. In particular, a number of experimental results attribute the majority of dielectric loss to one or several of the devicesubstrate, substrate-air, and device-air interfaces, rather than the bulk dielectrics [2][3][4][5][6][7][8][9][10][11] .
State-of-the-art superconducting qubits are fabricated by patterning an organic resist with e-beam or optical lithography to create a liftoff mask, followed by shadow evaporation of the aluminum layer [12][13][14][15][16][17][18] . Inevitably, this approach introduces contamination to the various interfaces 5 . This includes organic residues from the resist, contamination from the solvents that are required for the resist development after e-beam exposure, and those required for the lift-off process after metal deposition. Furthermore, degassing of the organic mask during metal deposition can lead to additional contamination.
In order to investigate the problems associated with residual contamination and eventually suppress it, we have developed a new nanofabrication technique for superconducting qubits (Fig. 1). Our technique replaces lift-off of an organic lithography layer with stencil lithography 19 based on free-standing silicon shadow masks fabricated from siliconon-insulator (SOI) wafers. Consequently, device substrate preparation becomes completely independent from the mask fabrication. As a result, the nanofabrication-related contamination is significantly reduced, and more important, controlled studies of surface dielectric losses as a function of surface preparation are now possible. Moreover, the inorganic mask is compatible with high-temperature processes, such as deposition of refractory metals and substrate annealing, which could be performed in situ. The silicon mask is free-standing, and thus can be removed from the target substrate at the end of the process and reused for subsequent depositions. It is also tension-free and therefore has higher mechanical stability relative to other possible stencil methods.
The  Fig. 2(a). The fabrication process starts by creating spacers to control the distance between mask and device substrate. The wafer was spin coated at 1000 rpm for 2 minutes with hydrogen silsesquioxane (HSQ), which is a negative inorganic e-beam resist [ Fig. 2  To demonstrate this new nanofabrication method, we focused on a mask design that is suitable for aluminum 3D transmon qubit 14 fabrication. Fig. 3 is a simplified schematic describing the metal deposition method. The large rectangular apertures correspond to the capacitor pads and the narrow slits to the leads that will form the Josephson junction of the transmon. The deposition process requires the ability to tilt and rotate the mask-wafer stack with respect to the evaporation source, similarly to that employed in the so-called "Manhattan" process 22 . The first deposition is performed with the stage rotated parallel to the left slit (ϕ = −45 • ) and tilted by angle θ , as shown in Fig. 3(a,b) and determined by considerations below. By selecting the width of the junction slits to be much smaller than the thickness of the suspended silicon membranes, and selecting θ accordingly, aluminum is deposited through the left slit and lands on the sidewalls of the right slit [ Fig. 3(b)]. To accomplish this, the minimum tilt angle should satisfy |θ | > arctan ( w /t), where w is the width of the slit and t the thickness of the silicon membrane. During the first deposition, the two capacitor pads and the first junction lead are formed, as shown in Fig. 3(c). An in situ oxidation step is then performed to create the tunnel barrier of the junction. A final (second) aluminum deposition with the stage rotated parallel to the right slit (ϕ = 45 • ) and tilted by θ creates the second junction lead along with another aluminum layer on both capacitor pads [ Fig. 3(c)]. Each fabricated mask contains multiple suspended silicon membranes patterned in that way. In Fig. 4(a-c), scanning electron microscopy (SEM) images of a single silicon membrane of a mask are shown. In every membrane, the capacitor pad apertures have dimensions of (530 × 480) µm 2 . We designed the width of the junction lead slits such as it gradually reduces in order to minimize possible conductive losses from otherwise long and narrow aluminum leads [ Fig. 4(b)]. We vary the minimum width of the junction lead slits w, from 200 to 400 µm, in order to create transmons with different junction area from the same mask. Narrower slits would require further optimization of the DRIE process, as well as thinner silicon membranes 23 . In order to increase the mechanical stability of the suspended silicon structure after etching, we opted to end the lead slits well before their crossing point. This imposes an additional condition that the tilt angle satisfies |θ | > arctan( d /h) for the two aluminum junction leads to overlap, where h is the mask-substrate separation. The silicon membrane of 5 µm thickness provides the necessary bending rigidity which further increases the mechanical stability of the suspended structure. Much thinner silicon would require a modified mask design with in-plane bridges across the slits. In Fig. 4(d) SEM image of a (200 × 200) µm 2 and 1 µm thick crosslinked HSQ spacer is shown. Arrays of such spacers across the mask are meant to define h and prevent possible adhesion of the mask on the device substrate due to Van der Waals forces. With the mask shown in Fig. 4 we fabricated arrays of 3D transmons 14 on 200 µm-thick, 100-mm diameter c-plane sapphire wafers. The sapphire substrates were cleaned in Nmethyl-2-pyrrolidone (NMP) at 90 • C for 10 min, sonicated consecutively in NMP, acetone, and isopropyl alcohol (IPA) for 3 min each, and then dried with nitrogen. All metal deposition and oxidation steps were performed in a Plassys UMS300UHV multichamber electron-beam evaporation system without breaking vacuum in-between steps. After reaching a base pressure less than 5 × 10 −9 torr, we evaporated 30 nm aluminum at ϕ = −45 • and θ = 20 • at 1 nm/min rate. We then oxidized the aluminum in situ with a O 2 /Ar (3:17) mixture for 15 min at 100 torr to create the tunnel barrier of the junction. A second evaporation of 40 nm aluminum was done at ϕ = 45 • and θ = 20 • . A final capping oxidation with a O 2 /Ar (3:17) mixture for 5 min at 50 torr was then performed. The same mask was employed multiple times on different sapphire wafers. The wafers were diced in (8 × 3) mm 2 chips, each containing a single transmon. To do so, we spin coated the wafers with a SC-1827 photoresist layer at 1500 rpm for 2 min and baked it at 90 • C for 9 min. This acts as protective layer against substrate debris damaging the devices during dicing. The resist was stripped at the end of the dicing process using sequentially NMP, acetone and IPA. Although the adoption of dicing resist is a common and convenient practice, it contradicts the purpose of our proposed technique which is to minimize fabrication residues, especially those coming from organic resist. However, the process of partitioning a wafer into smaller chips is independent of the fabrication of superconducting qubits at wafer-level, the main focus of our technique. The development of a reliable cleaving technique, which fundamentally does not require protective resist, would be essential for the full elimination of residues on the devices. Nonetheless, acknowledging the above limitation, we tested these devices in order to investigate whether our fabrication technique produces functional transmons.
Here, we present results for six transmons (A-F) derived from two independent sapphire wafers. In Fig. 5(a), optical images of qubit B are shown, where one can identify two aluminum layers that correspond to the two distinct evaporation steps. The double-lead pattern is the expected result of the double evaporation for a wide slit and does not affect the functionality of the devices. Nonetheless, the distance s between them provides an estimate for the effective masksubstrate separation of h eff = s /tanθ ≈ 30 µm. This value is much larger than the thickness of the HSQ spacers (1 µm). We attribute this to built-in residual compressive strain in the silicon device layer of the SOI wafer 24 , which leads to buckling of the silicon membranes upon their release from the Si/SiO 2 substrate. Nevertheless, a notable characteristic of our mask design is that the junction overlap area is approximately independent of the mask-substrate separation, as it is only defined by the width of the two slits. This is contrary to the results of the Dolan-bridge technique 12 , in which the junction area depends on both the mask substrate separation and the width of the slits. We further characterized the devices by taking atomic force microscopy (AFM) images of their junctions [ Fig. 5(b)]. We believe that the asymmetry of the widths of the junction leads is due to misalignment from the intended rotation angle ϕ and fabrication variances of the mask aperture width. A characteristic of this technique is that the deposited metallic films have a softer edge profile compared to traditional lift-off-based fabrication technologies. This is primarily due to diffusion of the deposited material on the clean substrate 19,25 .
We tested the devices in a dilution refrigerator with base temperature of ≈ 20 mK, adopting a standard circuit quantum electrodynamics (cQED) architecture in the dispersive readout regime 26 . The chips were mounted in an aluminum 3D rectangular-waveguide cavity 14 with fundamental mode at frequency ω r /2π ≈ 9.1 GHz. For qubits A, B, and C the external coupling rate of the cavity was set at κ/2π = 5 MHz and a waveguide Purcell filter (WR-90) with cut-off frequency at ω c /2π ≈ 6.6 GHz was implemented to minimize qubit radiative losses 27 . For qubits D, E, and F the coupling rate was set at κ/2π = 0.38 MHz minimizing the need for a Purcell filter. The measured properties for each qubit are presented TABLE I. Measured transmon qubit parameters. From left to right, junction normal-state conductance G N , qubit transition frequency ω ge , anharmonicity α = ω ge − ω ef , cross-Kerr χ, energy relaxation time T 1 , T 2R Ramsey and T 2e Hahn echo dephasing times. The fitting uncertainty for the decay times is up to ±10%. When the range of variation between measurements exceeds the fitting uncertainty, it is given explicitly.  28 . However, its performance fluctuated in time significantly, which necessitates additional investigation to understand. Moreover, further experimental studies are required to determine whether the energy relaxation properties of the devices are limited by surface dielectric losses 6 , by nonequilibrium quasiparticle excitations 29,30 or other losses. The low T 2R Ramsey and T 2e Hahn echo dephasing times are attributed to residual thermal photon population in the 3D aluminum readout cavity modes 31 . Single tunnel junctions have been previously fabricated with free-standing shadow masks based on silicon nitride (Si 3 N 4 ) membranes 32,33 . However, in these efforts, the auxiliary probe-electrodes were fabricated in a separate step in advance. An advantage of free-standing membranes based on silicon, compared to Si 3 Ni 4 , is that they are nominally free from residual in-plane tensile stress. As a result, silicon masks are mechanically robust enough to implement complex asymmetric aperture designs, allowing for better control of the Josephson junction area independent of mask-substrate separation. Additionally, large and small features can coexist on the same membrane. This provided us the means to fabricate tunnel junctions and the necessary auxiliary circuitry of a superconducting qubit device, such as the large capacitor pads of a 3D transmon qubit, using a single free-standing mask, reducing fabrication residues on the entire qubit device. Furthermore, our technique eliminates the need to align the tunnel junction with respect to the auxiliary circuitry. Inorganic shadow mask based on Ge/Nb bilayer have also been used for the fabrication of aluminum tunnel junctions by Welander et al. 34 . In their work, Ge/Nb thin films are deposited and processed directly on the device substrate which could potentially introduce additional contamination relative to free-standing inorganic masks.
In conclusion, we have developed a nanofabrication technique for superconducting qubits that is based on inorganic free-standing silicon shadow masks, fabricated from SOI wafers. We fabricated aluminum 3D transmon qubits with these masks and performed preliminary observations of their coherence properties. Our work addresses the residual contamination drawbacks inherent to e-beam and optical lithography techniques, providing a solid experimental platform to better understand, control and potentially minimize surfacedielectric losses in planar superconducting circuits. This technique accomplishes full decoupling of the mask fabrication from device substrate preparation, and thus minimizes crosscontamination between the mask and the device substrate. Systematic investigations of the effect of substrate treatment on surface dielectric losses, without the restrictions imposed by organic resist processes are made possible. A key advantage of inorganic masks is their ability to sustain high metal deposition temperatures. To this end, free-standing silicon shadow masks hold promise as a suitable technique to fabricate high-quality superconducting qubits based on refractory materials with larger superconducting gap, such as niobium. In addition, high temperature substrate annealing 8 can now be achieved in situ, under high vacuum, just before metal deposition, to further improve the surface properties of the device wafer. Finally, this technique is fully compatible with the fabrication of planar superconducting resonators, bringing to these necessary auxiliaries of tunnel junctions all of the aforementioned advantages.
We acknowledge insightful discussions with Michael Rooks, Michael Power, Shantanu Mundhada, Chan U Lei and Andrew Saydjari.