Fan-out enabled spin wave majority gate

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the $3$-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.

Fan-out enabled spin wave majority gate and demonstrated the SW power dependency of this phenomenon. However, this concept splits the SW energy and cannot provide SW replication, which is crucial for gate fanout achievement.
In view of the above, it can be concluded that SW based computing with potential ultra low energy consumption cannot become reality without gate intrinsic fanout capabilities. Here, we overcome this challenge and introduce a generic SW Majority gate structure that provides natural fanout support. Our structure is based on an area efficient 3-input Majority ladder-shaped SW gate structure that is able to provide a maximum fanout of 2. This concept has been validated by means of micromagnetic simulations with the Object Oriented Micromagnetic Framework (OOMMF).
Generally speaking, the proposed gate can operate with any SW type, however, each SW type has its proper dispersion relation, which plays a crucial role in the actual gate design. Magnetostatic Spin Waves (MSW) can be classified into three limiting cases: Magnetostatic Surface Spin Wave (MSSW), Backward Volume Magnetostatic Spin Wave (BVMSW), and Forward Volume Magnetostatic Spin Wave (FVMSW) 26 . Depending on the wave propagation direction, BVMSW and MSSW exhibit different dispersion relations. This complicates the circuit design because similar SW propagation in both horizontal and vertical directions is required. For FVMSWs, which propagate in a perpendicular plane to the static magnetization orientation, SW exhibit the same dispersion relation regardless of the wave vector orientation. In this view, we rely on them in the gate design introduced in the following lines.
Different SW excitation (and detection) methods exist, e.g., microstrip antennas 27,28 , magnetoelectric cells [29][30][31] , spin orbit torque 32,33 . A spin wave propagates through the waveguide with a wavelength λ , frequency f , amplitude A, and phase φ . Information can be encoded in its amplitude, phase, or both of them. If multiple SWs coexist in a waveguide, the computation can be performed using wave interference. Two waves with the same λ , A, and f can interfere constructively or destructively depending on their relative phase difference: (i) in-phase SWs interfere constructively and the resulting wave has doubled amplitude, (ii) out-of-phase SWs interfere destructively, and therefore cancel each other. If more than 2 equal λ and f SWs interfere, the result reflects a Majority decision, i.e., if more SW have φ = π (logic "1") than φ = 0 (logic "0"), the resultant SW has φ = π, and φ = 0 otherwise. This means that SW interference provides natural support for direct (no Boolean gates are required) Majority gate implementations. For example, a CMOS implementation of a 3-input Majority gate requires 18 transistors whereas a single magnetic waveguide is enough for the SW counterpart 11,16 . In the linear regime, it is possible to have simultaneous propagation of spin waves with different frequencies. The information can be en-Fan-out enabled spin wave majority gate coded in the phase of the spin wave at each and every frequency, therefore, SW gates inherently enable parallel computation on shared hardware resources. Additionally, if the involved waves have different amplitude, they still constructively or destructively interfere depending on phase difference. However, this generates multiple SWs with different amplitude values, which could be beneficial for the realization of multi-valued logic gates. In the most general case, SWs with different amplitudes, phases, wavelengths, and frequencies can be excited and intricately interfere in the same waveguide. This provides promising alternative avenues towards novel, yet to be discovered, SW based computing paradigms and systems.
In this paper, we propose a 3-input Majority gate (MAJ3) that has a ladder-shape structure, as depicted in Figure 1. The inputs are excited at (I 1 , I 2 , I 3 , I 4 ) and the outputs are read from (O 1 , To obtain a proper interference pattern at the crosspoints, the waveguide width w has to be less than or equal to the wavelength λ . Also, the excited SWs should have the same amplitude A. In addition, all excited SWs are required to have the same frequency to achieve the desired interference pattern. We propose a generic device layout, its dimensions and some critical distances d i (where i=1,2,. . . ,7) are expressed in terms of spin wave wavelengths as indicated in Figure 1. For example, if λ wavelength SWs have to constructively interfere when they have the same phase and destructively otherwise, d 1 , d 2 , d 3 , d 4 , and d 5 must be equal with nλ (n = 1, 2, 3, . . .). If the opposite behaviour is targeted, d 1 , d 2 , d 3 , d 4 and d 5 must be equal with n 2 λ (n = 1, 3, 5, . . .). Moreover, to obtain a proper fanout of 2, i.e., outputs with the same energy levels, the structure has to be symmetric, thus d 1 to d 5 must have the same value.
In contrast with CMOS gates, SW gates can provide both direct and inverted output by properly adjusting the output transducer position versus the output interference point. In this way the direct and inverted result can be read at a distance of nλ (n = 1, 2, 3, . . .) and n 2 λ (n = 1, 2, 3, . . .) from the last interference, respectively. In our case, MAJ(a,b,c) and MAJ(a, b, c) are obtained at d 6 = d 7 = nλ (n = 1, 2, 3, . . .) and d 6 = d 7 = ( n 2 λ (n = 1, 3, 5, . . .), respectively, and both outputs exhibit the same energy because of the structure symmetry. the gate outputs are identical, thus, the 3-input Majority gate exhibits a fanout of 2. It is worthmentioning that I 3 has effect on O 2 as spin-wave signal excited at I 3 propagates through I 1 and I 2 .
Also, I 4 has effect on O 1 as spin-wave signal excited at I 4 propagates through I 1 and I 2 . In addition, spin wave excited at I 1 and I 2 face edges while its propagation to the output, in contrast to I 3 and I 4 , which have straight path to the outputs. Therefore, I 3 and I 4 are excited at lower energy than I 1 and I 2 as will be discussed further later in this paper.
It is worth-mentioning that I 3 has effect on O 2 as the SW excited at I 3 propagates through I 1 and I 1 . Similarly, I 4 has effect on O 1 spin-wave signal excited at I 4 propagates through I 1 and I 2 .
In addition, SWs excited at I 1 and I 2 face edges while they propagate towards the outputs while I 3 and I 4 generated SWs have straight path to O 1 and O 2 , respectively. Therefore, I 3 and I 4 are excited at lower energy than I 1 and I 2 as further discussed in the paper.
We note that if only one MAJ3 output is required the structure can be simplified: i) physically, by removing one of its vertical waveguides (arms) or ii) logically, by not providing an input signal to I 4 . Moreover, the gate fanout capabilities can be extended beyond 2 by vertically lengthening its arms. For example, if the outputs in Figure 2  input and output spinning angles are calculated as: where m x and m y are the x and y component of the magnetization, respectively.   I 2 = 0, and I 1 = 1) or (I 3 = 0, I 2 = 1 and I 1 = 0) the the normalized output MSA is higher than when (I 3 = 1, I 2 = 1, and I 1 = 0) or (I 3 = 0, I 2 = 0, and I 1 = 1) because I 2 is located further than I 1 and I 3 from the interference location. As a result, when I 1 and I 3 have the same state, they interfere constructively and then destructively with I 2 , which results in a larger magnetization angle.
An accurate evaluation of the proposed structure is not possible at this stage of development, especially for the energy and delay. That is mostly due to the missing excitation and detection cells figure of merit data. Thus, as the transducers are the dominant source for energy and delay, we chose to use the area as a metric to position our proposal versus existing state of the art.
In order to make a fair comparison with 12   in a required area of 0.0691 µm 2 , i.e., our proposal provides a 16 % area reduction at the gate level. We note, however, that at the circuit level the area savings are significantly more substantial, as in order to deal with a fanout of 2 gate output O the approach in 12 requires the replications of all the gates on O's cone of influence starting from the circuit primary inputs, and that for efficient logic synthesis of practical circuits gates with > 1 fanout are frequently necessary.
In order to compare with CMOS, we evaluated a 3-input Majority gate implemented in 15 nm technology with two NAND gates and one OR-AND-Invert (OAI) gate, at V dd = 0.8 V, 25 • C, and an output load capacitance of 20 fF. Our evaluation indicate that the 15 nm CMOS MAJ3 area is 0.688 µm 2 , thus a 12x larger area than the proposed SW MAJ3 gate.
In summary, we presented a novel fanout of 2 area efficient 3-input spin wave Majority gate (MAJ3). We validated two instances of our proposal by means of OOMMF simulations and evaluated the fanout quality by making use of the Magnetization Spinning Angle (MSA) as metric.
We calculated the normalized MSA values for the gate outputs and obtained negligible mismatch between them under all possible input combinations, i.e., a high quality fanout. We compared our proposal with MAJ3 SW, under the same material assumptions and utilization conditions, and 15nm CMOS state of the art counterparts in terms of area and demonstrated a 16 % and 12x less area, respectively. As a closing remark, we note that achieving > 1 fanout is an enabling factor for the realization of SW circuits, as it eliminates the otherwise required circuit replication associated with fanout nodes intrinsic to SW circuits produced by means of logic synthesis. Thus, the impli-Fan-out enabled spin wave majority gate cations of our proposal at the circuit level are a lot more substantial than at the gate level, both in terms of area and energy consumption.

ACKNOWLEDGMENTS
"This work has received funding from the European Union's Horizon 2020 research and innovation program within the FET-OPEN project CHIRON under the grant agreement No. 801055."

Data Availability Statement
The data that supports the findings of this study are available within the article.