Analysis of the eight parameter variation of the resonant tunneling diode (RTD) in the rapid thermal annealing process with resistance compensation effect Differential in near field limit: Application to

The rapid thermal annealing process is a key technology to control the parameters of the resonant tunneling diode (RTD) and to achieve high performance for the device. In this paper, the rapid thermal annealing process on the planar RTD has been investigated experimen-tally. In the experiment, the annealing sample chips of different annealed times have been recorded from the annealing equipment and their I–V characteristics have been measured accordingly. From the I–V characteristics, the negative resistance and the series resistance of the RTD can be obtained. Thus, the relationship between these parameters and annealing time can be established. Finally, by analyzing the concept of the resistance compensation effect, this study explains fully and in detail the dependency of the RTD parameter variation on the annealing time. V P and V i are significantly reduced, greatly lowering R S , which in return also reduces the heat loss of the circuit and the power consumption of the RTD digital circuits as well as the RTD terahertz oscillator. As V V decreases, negative resistance R N is increased, and thus, the output power of the RTD terahertz oscillator is increased. These results are very useful in the study of RTD devices and fabrication technology.


I. INTRODUCTION
The resonant tunneling diode (RTD) is a high speed negative resistance-type nano-device. [1][2][3][4][5][6] Terahertz (THz) electromagnetic radiation is generally composed of electromagnetic waves with frequencies of 100 GHz-10 THz. The wavelengths of THz waves fall between those of light waves and millimeter waves. They are characterized by strong penetration, high security, and good ARTICLE scitation.org/journal/adv orientation and can be used extensively in medical and exploration applications. 2 However, a coherent and high-power source operating at room temperature is indispensable in these applications. Terahertz wave sources are classified into optical wave sources and electrical wave sources. Optical THz products are available commercially, but they are expensive and bulky. Resonant tunneling diode (RTD) oscillators are electrical wave sources, which are coherent, solid-state, compact, and high-power sources operating at room temperature. Resonant tunneling diodes (RTDs) 4,7,8 are good candidates for electronic THz wave sources from the angle of RTD oscillator fabrication. Kanaya et al. 2 reported a 1.42 THz oscillation with a reduction in the RTD intrinsic delay. The same team reported a 1.55 THz oscillation through optimization of the antenna length. 9 A 1.98 THz RTD oscillator was fabricated with the optimum electrode thickness of 2 μm. 1 In Ref. 10, the authors used a conventional lumped-element equivalent circuit to analyze a RTD oscillator. However, the theoretical analysis showed that the oscillator frequency and RTD size were correlated negatively. By contrast, the device output power and RTD size were correlated positively. Thus, the fabrication of high frequency RTD oscillators remains a challenge.
In addition to the fabrication of resonant tunneling diode terahertz oscillators, the RTD has other applications as a negative resistance device. [11][12][13] Artificial intelligence (AI) is currently a research hotspot. [14][15][16][17][18] In Ref. 19, the proposed systems of differential equations with the piecewise linear approximation of the S-type I-V characteristics could be utilized in analytical and numerical research and development of neural networks, [20][21][22][23][24] i.e., one of the core components of artificial intelligence. The development of neurodynamic models in circuit design is an important task of modern neuroelectronics, in particular, in the field of brain-machine interface. For example, it is applied as an electrical switching (ES), which gives an abrupt, significant, and reversible change in the conductivity of an electric element under the applied electric field or a flowing current, in addition, in current-voltage (I-V) characteristics of the element, which contains areas with negative differential resistance (NDR), 25 created by the positive feedback of current (S-type I-V) or voltage (N-type I-V). [25][26][27][28] Although the fabrication techniques of the RTD have been researched for a long time, 29,30 some fabrication technologies, inclusive of very critical ones related to the RTD, have not been researched in depth or systematically. For example, there are some published papers on the RTD, 31 which shows a near vertical straight line representation in the negative region of I-V characteristics. The series resistance RS of the RTD is very large and its DC negative resistance RN would approach zero, which would affect the output power of the RTD in the circuits. The purpose of rapid thermal annealing processing for the RTD is to ensure the contact electrode layer AuGeNi and heavily doping layer n + -GaAs in realizing the alloy process in forming an ohmic contact structure with an extremely low resistance, hence the RTD series resistance (RS) can achieve a very low value. However, so far in our literature review, there are neither any convenient or quick methods for measuring the RTD series resistance nor monitoring the annealing process, and thus, the annealed RTD still holds a high value of RS. The structure of the PRTD used in this study and the annealing process detailed will be discussed in Sec. II. The annealing results will be presented in Sec. III. Section IV will investigate the measurement results accordingly.

II. EXPERIMENT
RTD devices include mesa RTD (MRTD) and planar RTD (PRTD). The MRTD is a traditional RTD, which is grown by using Molecular Beam Epitaxy (MBE) [32][33][34][35] or Metal-Organic Chemical Vapor Deposition (MOCVD) [35][36][37][38][39] processes. The MRTD is a vertical device, and emitter region (E), well, and collector region (C) are located at different levels of the vertical direction. Comparing with the PRTD, the advantage of the MRTD is that it is easier to obtain a larger Peak-to-Valley Current Ratio (PVCR), which translates into better circuit design, while the disadvantage is the difficulty of controlling the actual active area. Furthermore, the difficulty of the reproducibility process hinders its integration on a larger scale. The limitations of the lithography precision and lateral corrosion processes constrain further refinement and miniaturization of the active area. There are other technical issues, such as preparation of side leakage and ohmic contact wiring. 40 In order to solve the shortcomings of the MRTD, the n + -GaAs grown by MBE technology is used as the substrate for the material structure, and self-aligned Boron ion implantation is used as the device isolation for producing the PRTD.
The PRTD chips and the material structure of the PRTD used in this experiment are shown in Fig. 1 and Table I. Boron ion implantation creates electrical isolation. The emitter is located on the top of the device, which is easy to integrate with other devices. The PRTD produced facilitates the hybrid integration of the RTD   41,42 which greatly simplifies the whole process. The sub-well structure is used in the well structure to reduce the effective threshold voltage (Vi). The emitter sub-well structure and the collector sub-well structure are used to form a two-dimensional resonant tunneling with the well structure, thus improving the negative resistance I-V characteristics and PVCR. Spacer and Barrier structures are indicated in the diagram also. The key structures are shown in Table I. The emitter AuGeNi metal is used to mask the Boron ion implantation. n + -GaAs is used as the substrate for the RTD to avoid the longitudinal current. In addition, the Boron ion injection is terminated to the n + -GaAs substrate. After the back of the substrate is thinned, AuGeNi is sputtered on the back of the substrate as the collector electrode, and on the front of the PRTD as the emitter electrode.
In our experimental study, the annealing temperature is fixed at 380 ○ C (a constant), while the annealing time changes from zero to 90 s. The measurement of I-V characteristics for different annealing times would extract VP (peak voltage), VV (valley voltage), Vi (effective threshold voltage), IP (peak current), and IV (valley current) parameters directly from the I-V curve and calculating RS, 43,44 RN, and PVCR 45 can be done using the following equations: where Rex is the external resistance, This study has deduced the relationship of the above parameters with the time-varying annealing process. By analyzing these relationships with the concept of the resistance compensation effect of the RTD, 46 we can explain fully the variation of RTD parameters with the time-varying annealing process in detail.
The equipment used for the annealing process is a RTD-500 rapid annealing oven. The equipment has the tungsten halide lamp as a light thermal source with annealing temperature changed rapidly using a designed program. The temperature (T)-time (t) characteristics of the temperature rising section, constant temperature section, and temperature falling section can be designed by setting the program controller of the annealing equipment. In this study, two chips of 6 μm × 6 μm PRTD with the GaAs substrate labeled by sample A and sample B, respectively, are taken as sample chips. The annealing condition of 380 ○ C, 30 s in nitrogen has been chosen for every annealing stage followed by 15 s cooling until reaching the room temperature. In the actual annealing experiment, the cooling time is about 90 s. The T-t characteristics are shown in Fig. 2, in which the blue line shows the setting annealing by program and the red line shows the practical operating annealing process. The full experiment is taken per following sequence: After the first annealing stage is finished, while waiting for the chip temperature to fall near room temperature, the annealed chip is taken out from the annealing equipment, using probe to contact with the electrode of the chip. The I-V characteristic is measured by using a YB4810A curve tracer. After cleaning with deionized water by supersonic wave and drying by blowing nitrogen, the chip is taken into the annealing equipment again for the second stage of annealing and so on for a total of three times. In order to study the effect of over-annealing on the chips, we raise the annealing temperature to 390 ○ C, while the annealing time is still maintained at 30 s for the fourth annealing.  Figure 3 shows I-V characteristics of sample A of the annealed chips. Table II shows the parameters of the sample A chip extracted from Fig. 3. RS is calculated by Eq. (1) as Rex = 0.

III. EXPERIMENTAL RESULTS
The first annealing is a non-pulsed standard annealing. 47 When the number of pulses is reasonable, the experimental results show that the pulsed T-profile annealing is more beneficial to the performance optimization of the device than the non-pulsed standard annealing. Figure 4 shows the I-V characteristics of the annealed sample B chip. Table III shows the parameters of the sample B chip extracted from Fig. 4.

IV. DISCUSSION
Taking the eight parameters of the PRTD listed in Tables II  and III as the Y-axis and taking the annealed times as the X-axis, we can draw the curves of eight parameters as functions of annealing times of the stage or the total annealing time, as shown in Figs. 5 and 6.
From Tables II and III and Figs. 5  Refs. 46 and 48, IP and IV are determined by intrinsic negative resistance characteristics due to the resonant tunneling effect. In addition, from Ref. 44, we also find that IP and IV hold as a constant when RS changes. IP and IV are near constant as the energy band or the material structure of the RTD (including the width of the potential barrier and well, and the doping density of the emitter and collector layer) is not changed. In our experiment, the annealing temperature of 380 ○ C cannot make any changes on the material structure of the PRTD, so IP and IV are near constant. Since PVCR = IP/IV , PVCR is also a constant.

B. Over-annealing, R S decreases and |R N | increases as annealing time increases
For a different chip, the situation of decreasing RS is different. For the sample A chip, RS maintains a decreasing trend until over-annealing to present an apparent positive resistance (APR) 49 phenomenon and until reaching positive resistance RAPP 26.9 Ω. However, for the sample B chip, RS falls to the saturated value of 141 Ω for the first annealing, and still holds this saturated value near a constant until over-annealing, then RS starts to increase. The explanation of decreasing RS with annealing time is that at 380 ○ C, the Ge atom of AuGeNi will diffuse into the n + -GaAs layer more deeply with increasing annealing time, this effect will increase the donor impurity density in the n + -GaAs layer, so the ohmic contact resistance and RS will decrease. In Fig. 5 as |RNint| > RS, from Eq. (4), we can find that |RN| increases with decreasing RS.
C. V P , V V , and V i decreasing with increasing annealing time Both annealing chips show that VP, VV , and Vi decrease with annealing time except over-annealing. Since from Ref. 50, as RS occurs in the RTD, VP is proportional to RSIP, VV is proportional to RSIV , when IP and IV maintain to be near constant, then VP and VV will surely decrease with decreasing RS, for increasing annealing time. Since IP > IV , the decrease of VV (∝RSIV ) is not obvious compared to VP. From Ref. 44, the effective threshold voltage Vi is shown in the following equation: where Eacc/q and E dep /q are the potential drop of electrons in the emitter accumulation layer and collector depletion layer under the peak state for the RTD, respectively. E 0 is the energy level in the potential well, and Qm and C are the maximum electrical quantity in the potential well and the capacitance of the double barrier structure, respectively. All of these only consider the intrinsic factors of Vi. Considering a practical factor, such as the potential voltage drop introduced by contact resistance RC at the ohmic contact structure RCI, Vi is shown in the following equation: As PRTD chips are annealed and contact resistance RC decreases with annealing time, from Eq. (6), Vi will surely decrease.

D. Over-annealing phenomenon
The so-called over-annealing means that under more severe annealing conditions (such as over-high annealing temperature or over-long annealing time), the performances of annealed chips are deteriorated by the annealing process.
After over-annealing, RS of the sample B chip increases in the medium level from 140 Ω to 175 Ω, VP also increases a little from 0.78 V to 0.80 V, and |RN| decreases from 125 Ω to 100 Ω. This is a phenomenon of primary over-annealing. It indicates that the effect of annealing begins to run toward the opposite direction. RS of sample A increased obviously from 141 Ω to 250 Ω. From Ref. 50, when RS increases as large as to make |RNint| < RS, the remainder of RS compensation with R Nint is positive resistance RAPP. The APR 49 effect will happen. The experimental results on the over-annealing effect on both chips completely demonstrate the process of generation of APR by the fact of RN from −100 Ω hanging to RAPP = 26.9 Ω (for sample A) as well as presenting the I-V characteristics of VP > VV [see Fig. 3(e)]. At present, the concrete physical mechanism of over-annealing is yet to be determined and further work would be carried out. It may be related to non-uniform over-heating or slight oxidation of contact metal (could be due to the introduction of impurity to the nitrogen used). We yet to set up a gas monitoring equipment for measuring the oxygen content and distribution in the annealing equipment. Further study is required at a later stage for this work. Figure 7 shows the PRTD surface after over-annealing with some impurities and craze.

V. CONCLUSIONS
In this paper, based on the measurement of negative resistance parameters from the I-V curve of the PRTD with different annealing times, the variations of eight parameters as a function of annealing time have been studied and analyzed in detail with full explanations using the variation of eight parameters with annealing time and using the concept of the resistance compensation effect of the RTD device. IP, IV , and PVCR are near constant in all of the annealing processes. VP and Vi are significantly reduced, greatly reducing RS, which will reduce the heat loss of the circuit and the power consumption of the RTD digital circuits and RTD terahertz oscillator. As VV decreases, negative resistance RN increases, increasing the output power of the RTD terahertz oscillator. The annealing condition for the PRTD is more severe than that of the MRTD. In actual fact, the experimental results of the rapid thermal annealing process that takes on the PRTD are very similar to those of the MRTD, i.e., the work is suitable for both types of RTD devices. The work done here is of great significance and novelty to the study and further understanding of the RTD fabrication technology.