Monolayer MoS 2 -based nonvolatile transistors with a titanium nitride in the gate

Low-power, nonvolatile transistors are demanded in the digital electronics development. In our work, molybdenum disulfide (MoS 2 ) acts as the channel material integrated with TiN, which is used as a floating gate to build a floating gate transistor. Our transistor exhibits a large hysteresis of 4 V (Vd = 0.1 V), high on/off ratio of 10 5 , and symmetry writing and erase voltage. The excellent device characteristics such as nondestructive data readout, low operation voltage, and wide memory window inherent in single-layer MoS 2 show their great potential to be applied in nonvolatile memory cells.

Nonvolatile memory cells have potential advantages in secure and fast data storage devices. Energy consumption and floating gate memory miniaturization are demanded to achieve large-scale integration and higher packing density components. 1,2 Monolayer molybdenum disulfide (MoS 2 ) has many natural advantages such as direct bandgap, a relatively small dielectric constant, and atomic thickness, which help to suppress short channel effect, beneficial for reducing power dissipation. [3][4][5][6][7] While MoS 2 acts as the channel of a memory transistor, its large on/off ratio can differentiate various memory states. Doped hafnium oxide (HfO 2 ) is considered as the promising candidate for Si-based ferroelectric fieldeffect-transistors (FeFETs) in which some Hf ions were replaced with zirconium atoms. [8][9][10][11] Doped HfO 2 films are thin, atomic layer deposition (ALD)-friendly, compatible with the high aspect ratio three-dimensional capacitor structure, and immune to defect generation. 12 The dielectric constant of hafnium zirconium oxide (HZO) is higher than that of HfO 2 . The higher the gate dielectric constant, the better the gate control ability of the device. Hence, the high dielectric constant of gate dielectric in HZO helps to reduce the operating voltage of the device. In addition, the ALD grown HZO film with the titanium nitride (TiN) electrode was boosted by the asymmetric strain provided by the TiN electrode. In our work, the monolayer MoS 2 channel with TiN in the gate is adopted for the fabrication of the floating gate memory-based transistor. A systematic study on the floating gate memory transistor is demonstrated; especially, the interface properties and the capacitance effects are studied.
The process flow schematics for fabricating the device in this work are shown in Fig. 1(a). TiN was grown from Physical Vapor Deposition (PVD) on SiO 2 /p++ Si substrates. Following the deposition of TiN, HZO was grown using ALD. HZO films were grown in a 1:1 Hf:Zr ratio, and TiN was grown on HZO. TiN was patterned with photolithography and lift off to form a floating gate. Then, 8 nm HfO 2 was deposited by ALD. Chemical vapor deposition (CVD) monolayer MoS 2 was transferred on HfO 2 covered with a sacrificial Al 2 O 3 layer by ALD. Monolayer CVD-grown MoS 2 was characterized with the Raman spectrum, and thicknesses were confirmed. Followed by metallization with 50 nm Ti and 70 nm Au, lift-off was performed in acetone. Finally, the annealing process was performed at 250 ○ C in the Ar environment for 2 h to improve the contact and remove the photoresist residue on MoS 2 . The channel length of the fabricated back-gate device is 10 μm, and the width of the device is 380 μm.
The schematic of the floating gate memory-based monolayer MoS 2 transistor is shown in Fig. 1(d). The image of the device is shown in Fig. 1(b). A representative microscope image of floating gate memory-based monolayer MoS 2 transistors is shown in Fig. 1(c). The Raman spectrum in Fig. 1 13 In the equilibrium state (without bias), the carriers in MoS 2 and TiN cannot be exchanged with each other due to the blockage from the HfO 2 interlayer. When a positive voltage is applied on the gate, the MoS 2 channel generates electrons; in the meantime, the potential of electrons in MoS 2 becomes higher than the one in the TiN layer. Due to the potential drop in the HfO 2 layer, the effective barrier high of HfO 2 is lower and the electron in MoS 2 has a higher probability to tunnel through the HfO 2 barrier, causing an amount of electrons injected into the TiN trapping layer. The trapped electrons in the TiN layer will stay still after the voltage is removed, which modulates the residue carrier density in the MoS 2 and leads to the shifting of V th (threshold voltage) to positive voltage. Similarly, when a negative voltage is applied on the gate, the trapped electron in TiN has a higher potential and then tunnels back to the MoS 2 channel, as shown in Fig. 2(c). Figure 2(d) shows the transfer characteristics of the device with different drain voltages (the scan range of V G is from −3 V to +3 V). The forward and reverse sweeps demonstrate a large memory window of about 4 V under the different drain voltages. There are no obvious shifts in the transfer curves with different drain voltages, illustrating a stable electrical performance for these floating gate transistors. For nonvolatile memory usage, we define the 3 V at the gate for the "write" voltage and the −3 V for the "erase" voltage. Those operations of gate voltage modulate the channel current for the device after withdrawing the gate bias. The symmetry of voltages for "write" and "erase" helps to reduce the power consumption and is beneficial for circuit design. We believe that the voltage for the trapping and detrapping operation depends on the tunneling barrier of the electron into and out of the trapping layer. The conduction band offset (CBO) between MoS 2 and HfO 2 is about 1.7 eV 14 and 1.8-2.1 eV between the TiN trapping layer and HfO 2 . The TiN interlayer was chosen due to the relatively small difference between the CBO of the MoS 2 /HfO 2 and that of the TiN/HfO 2 , which is smaller than that of other metals which have been used as the trapping layer. 1 Therefore, a relatively symmetrical voltage of ±3 V on the gate to transfer the electron between the trapping layer and the channel is realized. At the same time, the on/off ratio is high up to 10 5 , as shown in Fig. 2(d). All these demonstrate a sufficiently large memory window with strong potential for the data storage applications.
For a control device, we fabricated the HfO 2 /MoS 2 FET without a TiN top layer using the same fabrication process, as shown in Fig 3(d). Figure 3(b) presents the transfer characteristic of the 10 μm-long HfO 2 /MoS 2 FET without TiN/HZO/TiN. From the transfer curves in Fig. 3(b), we can see that when the gate voltage sweeps at room temperature from negative to positive voltage and then from positive to negative voltage, the hysteresis is about 0.1 V, much smaller than the device with a TiN top layer. Hence, the large hysteresis of about 4 V in the device with a TiN trapping layer is not from the interface traps or dielectric movable ions. Surface roughness and contact between metal and MoS 2 are also examined. Figure 3(c) shows the atomic force microscope image of the deposited HfO 2 . As shown in this figure, the rms is 0.874 nm. It indicated that the HfO 2 layer is compact and well uniform, indicating that there is a uniform deposition of HfO 2 followed by the monolayer MoS 2 as a channel layer. To verify the contact quality of these devices, I DS -V DS curves are studied under a small bias (V G is from −2 V to 2.5 V). Figure 3(a) presents a nearly linear fitting of the curves even under a relatively small drain-source bias. The curve indicates the formation of ohmic contacts between metal and monolayer MoS 2 . The current of the MoS 2 /HfO 2 FET, at the level of 16 μA for a 2 V bias, corresponding to a total series resistance of 125 kΩ shows that efficient charge injection from the metal to MoS 2 is possible. In the future, graphene contacts may be a promising solution to improve source/drain contacts with MoS 2 , and it is expected to obtain higher output current when applying lower voltage.
In general, the charge trapping at the MoS 2 /HfO 2 interface will degrade the "low" state current and subthreshold swing (SS). Therefore, a high quality HfO 2 /MoS 2 interface is demanded. The control device in Fig. 3(b) shows a small hysteresis of about 0.1 V and SS of about 104 mV/decade, which indicates a good interface property in our device. Notably, 10 nm Al 2 O 3 was also deposited on the surface of the MoS 2 to eliminate surface contaminations. As a passivation layer, Al 2 O 3 can also be beneficial to reduce the interface charge. It is also demonstrated that the on/off ratio increases with the drain voltage. As predicted above, MoS 2 /HfO 2 interface charges have less effect on the memory windows.
These results demonstrate that the window of the memorybased monolayer MoS 2 transistor with TiN is mainly caused by the storage capability of the TiN floating gate layer, not by the charge trapping in the interface between HfO 2 and MoS 2 .
In summary, a method to fabricate high-performance monolayer MoS 2 transistors with the TiN floating gate is demonstrated. Importantly, the device demonstrates a stable and symmetric hysteresis window of about 4 V and high on/off ratio of 10 5 . The effect of interfacial quality on the electronic behavior and memory characteristics of memory-based monolayer MoS 2 transistors are studied. All these excellent device characteristics as well as the easy architecture process indicate the technology potential of the single-layer MoS 2 based floating gate transistor for the development of future energy saving memory devices.

ARTICLE scitation.org/journal/adv
See the supplementary material for a summary of the details for liquid-assist transfer of chemical vapor deposition (CVD) synthesized 2D MoS 2 and fabrication of a typical 10 μm-long MoS 2 /HfO 2 FET.