III-V-on-Si photonic integrated circuits realized using micro-transfer-printing

Silicon photonics (SiPh) enables compact photonic integrated circuits (PICs), showing superior performance for a wide variety of applications. Various optical functions have been demonstrated on this platform that allows for complex and powerful PICs. Nevertheless, laser source integration technologies are not yet as mature, hampering the further cost reduction of the eventual Si photonic systems-on-chip and impeding the expansion of this platform to a broader range of applications. Here, we discuss a promising technology, micro-transfer-printing (μTP), for the realization of III-V-on-Si PICs. By employing a polydimethylsiloxane elastomeric stamp, the integration of III-V devices can be realized in a massively parallel manner on a wafer without substantial modifications to the SiPh process flow, leading to a significant cost reduction of the resulting III-V-on-Si PICs. This paper summarizes some of the recent developments in the use of μTP technology for realizing the integration of III-V photodiodes and lasers on Si PICs. © 2019 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). https://doi.org/10.1063/1.5120004., s


I. INTRODUCTION
Silicon photonics (SiPh) is emerging as a promising platform for building complex and powerful photonic integrated circuits (PICs). Its high index contrast not only allows for ultracompact PICs but also results in an enhanced light-matter interaction enabling efficient active devices such as high speed modulators. The inherent advantage of complementary metal-oxide-semiconductor (CMOS) compatibility of SiPh processes allows for scalable and low-cost production of PICs on 200 mm or 300 mm wafers. Nevertheless, the complicated assembly of light sources with Si PICs leads eventually to a high product cost, impeding the use of Si PICs in a wider range of applications.
In the past years, great effort has been devoted to establishing a mature technology for realizing the cost-effective integration of III-V-on-Si lasers and other noninherent functionalities on Si PICs. Different approaches have been followed. Among the existing methods, the monolithic integration of III-V semiconductors on a Si substrate through heteroepitaxial growth is the ultimate integration approach. 1,2 However promising, this is still at an early stage, with much work to be done on the integration of these process modules in the SiPh process flow and demonstrating the reliability and performance of the resulting devices. From the hybrid integration approaches, flip-chip integration is mostly adopted in industry. This approach allows us to use the superior characteristics of readily fabricated devices such as III-V semiconductor lasers, amplifiers, and photodetectors (PDs) and allows for pretesting before assembly, enhancing the compound yield. The high alignment accuracy required in the flip-chip assembly process 3-6 makes it difficult, however, to scale up and reduce the cost of resulting PICs. Heterogeneous integration through die-to-wafer or wafer-to-wafer bonding has attracted a lot of attention in recent years to overcome this issue, as in this case the critical alignment of the III-V structure to the Si waveguide circuit is realized using wafer-scale lithographic processes. Some foundries are developing a CMOS process flow for the wafer-scale realization of III-V-on-Si PICs, where III-V dies are first distributed on a temporary carrier, e.g., a Si wafer, by a pick-and-place method and then integrated on the target SiPh wafer (after its front end processing) through wafer bonding, followed by a back-end process flow for the definition of the III-V structures and the back-end metallization stack. [7][8][9] In this case, the back-end process flow has to be modified to accommodate the III-V devices. In addition, the compound yield can be affected, as the III-V devices can only be tested after they have been integrated on the SiPh wafer. The simultaneous integration of different III-V materials/devices on a common substrate, while possible, 10 is also still challenging.
Micro-transfer-printing (μTP) is a novel integration technique developed by the Rogers group at the University of Illinois in 2004. 11,12 This technique allows for the manipulation of micrometer-sized thin films/thin film devices and enables the transfer of these thin film devices in a massively parallel manner (ensuring high throughput integration, as a single printing cycle only takes 30-45 s) from a source substrate to a target substrate with high alignment accuracy. By using this approach, the efficiency of the use of source materials can be significantly improved and different materials/devices can be intimately integrated on a common substrate. Moreover, this integration requires no modification of the SiPh back-end process flow, except for a local back-end opening where the devices need to be integrated. Similar to the flipchip-like assembly, μTP allows for prefabrication and pretesting of the devices on its native substrate prior to their integration on a target Si PIC wafer. The technique in principle also provides the possibility of the reuse of the III-V substrate, which can again lead to a cost reduction. A comparison of the pros and cons of these aforementioned approaches is summarized in Table I. In this paper, we review our recent results on the heterogeneous integration of III-V lasers and photodiodes on Si PICs through the μTP approach. Other groups have activities along similar lines. [13][14][15][16]

II. CONCEPT OF THE μTP TECHNIQUE
The μTP process is schematically illustrated in Fig. 1. 17 A polydimethylsiloxane (PDMS) stamp with a post array (or a single post) whose size and pitch match those of the device array arranged on the source wafer is used to pick up and transfer these devices onto a target wafer. The stamp is fabricated through casting PDMS on a Si master mold and after releasing, laminating it on a glass carrier wafer. Over 300 000 printing cycles 18 have been demonstrated with such stamps. The release of the prefabricated devices from their native substrate is enabled by incorporating a sacrificial layer in the epitaxial layer stack between the device layer and the substrate, which can be selectively etched. As indicated in Fig. 1(b), devices are patterned on the III-V source wafer and are protected with an encapsulation layer (typically a photoresist layer in the case of III-V devices) with local openings to access the release layer, which is then underetched (using FeCl 3 :H 2 O in the case of InP-based epitaxy), leaving the released devices or material coupons anchored  to the substrate by the tether structures while retaining registration. An example of a complex PIC that can be realized using this approach is schematically shown in Fig. 2, where two III-V-on-Si tunable lasers are cointegrated with microheaters and germanium (Ge) PDs by μTP of prefabricated III-V amplifier structures in a recess that was defined on the Si PIC. The pick-up and printing operation are enabled by setting the peeling velocity of the stamp, due to the rate-dependent adhesion strength of the device(s) to the stamp. 19 In the pick-up step, the PDMS stamp is first aligned and laminated to the desired devices on the source wafer and is then pulled back at a high velocity. This results in a relatively high adhesion strength of the devices to the stamp, thereby breaking the tethers and attaching the devices to the stamp. The devices are then aligned to and automatically printed on the target wafer by laminating the stamp to the target wafer and slowly retracting the stamp. This results in a low adhesion strength between the devices and the stamp and leaves the device attached to the SiPh target wafer (either using van der Waals forces 20 or with an adhesive bonding agent 21 ) together with the encapsulation layer. The alignment is enabled by locating the center of the codesigned fiducial marks on both the source device and target substrateas seen through the transparent PDMS stamp-through a pattern recognition function. This way ±1.5 μm (3σ) alignment accuracy is achieved when printing devices in large arrays. We have observed in our experiments that better alignment accuracy can be achieved by reducing the size of the array. If deep submicron alignment accuracy is required one can make a compromise by μTP material coupons on the target substrate, followed by a contact UV lithography process, 22 similar to what is done in die-to-wafer bonding approaches. The final processing steps on the Si target wafer consist of removing the encapsulation, passivating the device, and electrically connecting the III-V optoelectronic components to the rest of the PIC.

III. μTP OF III-V PHOTODIODES ON Si PICs
High-performance PDs are essential elements in Si PICs. Different Ge PD structures with low dark current, high responsivity, high avalanche gain, and high bandwidth have been demonstrated. Nevertheless, in specific applications which, for example, require wavelength duplexing or polarization-independent optical detection or which are to operate outside the classical telecommunication wavelength window, III-V semiconductor photodiodes are required. As an example, a transceiver for Point-to-Point Fiber-To-The-Home (PtP FTTH) optical networks at the central office side is demonstrated. In this transceiver, an O-band III-V PD that was proposed for the reception of the O-band upstream data signal in a polarization-independent way was integrated on a SiPh fiber-to-chip grating coupler. Duplexing of the upstream (1310 nm O-band) and downstream (1550 nm C-band) signals is realized by choosing the cut-off wavelength of the III-V photodiode to be 1.37 μm. 23 Here, the μTP technique is used for the integration of such O-band III-V PDs on a SiPh platform for realizing a 4-channel PtP FTTH transceiver. The concept of the transceiver is schematically illustrated in Fig. 3, where microring modulators are used to imprint the downstream signal on the C-band optical carrier.
The epitaxial layer stack used in this demonstration consists of a 1 μm thick intrinsic InGaAsP absorbing layer with a cut-off wavelength of 1.37 μm sandwiched between p-doped and n-doped InP cladding layers. In addition, a 1 μm thick InGaAs layer was grown between the device layer stack and the InP substrate to enable releasing the prefabricated PDs. Figure 4(a) depicts the III-V source wafer with a dense square array of PDs with pitch of 100 μm. Figure 4 A detailed description of the fabrication process can be found in Ref. 24. In the printing step, the U-shape P-type metal contact and grating coupler itself were used as fiducial markers for the alignment by the pattern recognition software. Figure 4(c) shows the final realized 4-channel transceiver array. The responsivity of the integrated PDs for the O-band signal was measured to be 0.39-0.46 A/W, which is four orders of magnitude higher than that for the C-band signal, enabling the duplexing of both signals without substantial cross talk. 10 Gbps operation was successfully demonstrated for both upand downstream data signals. A similar concept was also implemented for a C-band SiPh 4-wavelength channel receiver as shown in Fig. 5. In this case, a 1 μm thick intrinsic InGaAs layer instead of the InGaAsP layer is used for the C-band signal detection, while the rest of the layer stack remained the same. This receiver achieved 25 Gbps operation. 25 Moreover, parallel μTP using a stamp with 4 posts was demonstrated, resulting in a device printing yield of 98.8% (83 over 84 printed devices). 26 The resulting PIC with integrated PD array is shown in Fig. 6. Uniform performance was observed in the characterization, where, for example, the PDs integrated on 1D grating couplers show a waveguide-referred responsivity of 0.553 A/W at 1570 nm with a standard deviation of 0.033 A/W. Other than these classic III-V photodiodes, GaAs metal-semiconductor-metal (MSM) PDs and Ge PDs were also successfully integrated on a target wafer of interest (comprising passive SiN and Si waveguide circuits, respectively). 27,28

IV. μTP INTEGRATION OF ETCHED-FACET LASERS ON Si PICs
Several different approaches are currently being considered for the integration of laser sources on SiPh PICs through μTP. One approach that is similar to the coupling scheme used for flip-chip integration is shown in Fig. 7, where a prefabricated etched-facet Fabry-Pérot laser is transfer-printed into a predefined recess on the SiPh target wafer with the bottom of the trench reaching the Si substrate. By properly designing the III-V epitaxial stack and the dimensions of the laser waveguide cross section, the laser output directly couples to the Si PIC through a codesigned spot-size-converter defined in the 220 nm thick Si device layer. 29 The III-V epitaxial layer stack used for this demonstration consists of 4 InGaAsP quantum well/barrier pairs (6 nm/12 nm) sandwiched between two 50 nm thick InGaAsP separate confinement heterostructure layers. A socalled Si trident taper structure which, as shown in Fig. 7, effectively expands the mode size in the lateral dimension is used to interface with the laser. A 1950 nm thick n-InP cladding layer and 100 nm undoped InP layer are used to level the III-V active region with the Si device layer. A 500 nm thick InGaAs sacrificial layer is incorporated beneath the InP bottom cladding layer to release the prefabricated devices.
As the laser cavity has to be formed on the III-V source wafer by etching the facets, a dry etch process was used in the laser definition to have a smooth and vertical sidewall. A gold deposition on the  etched rear facet was used to enhance the reflectivity. The footprint of the coupon is 50 × 400 μm 2 . Note that the etching of the InGaAs release layer in a FeCl 3 aqueous solution is anisotropic. 30 Therefore, to accelerate the undercut and obtain a flat bottom surface (given the finite selectivity in etching InGaAs with respect to InP), the coupons are usually arranged at a 45 ○ or 135 ○ angle with respect to the cleave directions of the III-V wafer. Otherwise, a pyramid-shape bottom surface will be formed after the long release etch, as shown in Fig. 8, hampering the printing on the flat Si substrate. In this proof-of-concept demonstration, the devices were printed one by one onto the target SiPh chip without using an adhesive bonding agent. The direct attachment of the III-V device to the Si substrate provides an enhanced thermal dissipation due to the high thermal conductivity of Si. 31 Figure 9(a) shows a microscope image of the resulting PIC with integrated lasers, 29 where the inset depicts the codesigned marks on the III-V laser coupons and the Si photonic target wafer used for the alignment through pattern recognition. 17 out of 20 devices were printed on the target PIC with a resulting absolute alignment accuracy within 1 μm. All of the integrated lasers exhibited lasing and milliwatt-level waveguidecoupled optical power was successfully demonstrated, as shown in Fig. 9(b). However, the spread on the laser characteristics shows that there is still room for improvement in the laser and coupling uniformity.

V. μTP INTEGRATION OF III-V-ON-Si EVANESCENT LASER STRUCTURES
A. Alignment-tolerant adiabatic taper structure An alternative option for laser realization is evanescent coupling of the III-V gain waveguide to the Si waveguide circuit using an adiabatic taper structure. This, however, typically requires thicker Si waveguides (400 nm or above) in order to achieve the phase match condition and thus allows for an efficient mode conversion between the III-V/Si and Si waveguide. Here, a waveguide platform consisting of a 400 nm thick crystalline Si device layer on a 2 μm thick buried oxide layer is used. The waveguide circuits are defined by a single 180 nm etch step using dry etching and planarized using a SiO 2 chemical mechanical polishing process down to the Si device layer. The linear III-V/Si taper structures that have been widely used in evanescently coupled III-V-on-Si devices realized through die-to-wafer bonding require a stringent alignment accuracy (typically less than 300 nm), however. 32 In order to accommodate the alignment accuracy provided by the μTP system, we designed a coupling taper structure that can tolerate up to 1 μm lateral misalignment. Figure 10 schematically illustrates the difference between In this way, the disturbance to the guided optical mode induced by any misalignment of the III-V taper structure is significantly reduced, at the expense of a reduced confinement in the III-V active region (1.43% per quantum well in the traditional taper structure vs 0.75% per quantum well in the alignment tolerant scheme). The optical mode in the III-V/Si taper is converted to the fundamental mode in the underlying Si waveguide through a linear III-V taper structure. Then, the broad Si waveguide is narrowed down and connected to a 650 nm wide single TE mode waveguide. The structure also shows potential for high saturation power semiconductor optical amplifiers (SOA) due to the reduced confinement in the active region. 33,34 Figure 11 shows the calculated coupling efficiency (TE polarization-1.55 μm wavelength) as a function of the length of the III-V taper structure for different BCB bonding thicknesses with a given lateral misalignment of 1 μm. The III-V taper tip width was set to be 400 nm, while it was found by simulation that even an 800 nm wide taper allows for complete mode conversion. The length of the linear III-V taper structure was set to be 180 μm to enable a highly alignment-tolerant and process-variation-tolerant coupling. Figure 12 shows the optical mode conversion over the taper structure, where the lateral displacement is set to be 1 μm. The III-V taper tip is 400 nm wide, the III-V taper structure is 180 μm long, and the BCB bonding layer is 20 nm. As expected, the hybrid mode converts to the fundamental Si mode along the taper structure.

B. Prefabrication of μTP-compatible SOAs on their III-V substrate
The III-V epitaxial layer stack used for the integration of Cband SOAs/lasers consists of a 60 nm/200 nm intrinsic InP/n-InP bottom cladding, a 6 quantum well AlInGaAs active region and a 2 μm/285 nm thick p-InP/p-InGaAs top cladding. As demonstrated in Ref. 35, InAlAs is more suitable for use as the release layer. It provides a higher etch rate, an improved selectivity to InP, and an isotropic etching behavior in FeCl 3 based etchants, and a 500 nm thick layer is adopted for the release of the devices. The definition of the SOA follows the standard processing steps that were developed for the heterogeneous integration of III-V-on-Si devices based on die-to-wafer bonding. In order to obtain a "V" shape mesa cross section and thus a narrow taper tip, an HCl-based wet etching of the p-InP was used and the taper structure was oriented along the [011] crystal axis. 22 Figure 13(a) shows the resulting 'V' shape InP mesa with a 400 nm wide bottom at the taper tip. To enable autoalignment in the μTP through pattern recognition, a pair of "L"-shaped fiducial marks was defined at the coupon ends during the p-InP mesa definition. The release was performed in a 3 ○ C aqueous FeCl 3 solution, and it took about 80 min due to the high etch rate of InAlAs. Figure 13(b) shows a microscope image of the released III-V SOA array on the source wafer.

C. μTP integration of III-V-on-Si DBR lasers
Distributed Bragg Reflector (DBR) lasers are demonstrated using the proposed tapered III-V SOA structure. The schematic layout of the DBR laser is illustrated in Fig. 14. The waveguide circuits were fabricated using an e-beam lithography process and a 180 nm single etch step into the 400 nm thick Si device layer. SOAs with an overall length of 1360 μm, including the taper structures, were micro-transfer-printed on the target PIC using a 20 nm thick BCB bonding layer. The laser cavity is 1800 μm long, formed by a pair of sidewall-corrugated DBRs 36 (period 247 nm, 900 periods, and 600 periods for the rear and front DBR, respectively). All of the coupons were successfully printed on the target PIC, as shown in Fig. 15(a), followed by final metallization through a standard liftoff process. The series resistance of the fabricated devices is about 6 Ω. A waveguide-coupled power over 5 mW is obtained at 20 ○ C, as shown in the Power vs Current (P-I) measurement in Fig. 16(a). The laser spectrum recorded at a bias current 290 mA is illustrated in Fig. 16(b), showing up to 40 dB side mode suppression ratio.

D. μTP integration of widely tunable III-V-on-Si lasers
In our earlier work, III-V-on-Si widely tunable lasers have been demonstrated on a 400 nm SiPh platform through die-two-wafer  bonding technology, 37 in which case the optical mode was fully transferred from the Si device layer to the III-V amplifier. The laser exhibited a 40 nm tuning range in the L-band and milliwatt-level waveguide-coupled output power. To facilitate the μTP-based integration of such a widely tunable laser, a 2 μm wide waveguide is now incorporated underneath the amplifier. As discussed above, this relaxes the alignment requirements at the expense of a reduced confinement of the optical mode in the gain region. The laser has a 1.16 mm long linear gain region, as depicted in Fig. 17 along with two mirrors consisting of a tunable double-ring Vernier filter and a broadband tunable reflector (implemented using a Mach-Zehnder interferometer and a loop mirror). Microheaters (not shown in the schematic) are integrated post transfer-printing on the ring resonators, the phase section, and the tunable reflector for laser tuning purposes. The overall cavity length is about 3.2 mm long, which results in a longitudinal mode spacing around 60 pm at a resonance of the Vernier filter. The ring resonators have a radius of 25 μm and 27.5 μm, respectively, leading to a combined Vernier FSR over 40 nm in the 1560 nm wavelength range, as a transmission spectrum through the Vernier filter shows in Fig. 18. The gap between the bus waveguide and the ring resonator waveguide (both are 650 nm wide) is 400 nm, which results in a loaded Q-factor of 34.5 × 10 3 and a drop port loss of 1.3 dB. In the fabrication, 1160 μm long SOAs (including a pair of 180 μm long taper structures and a 800 μm straight SOA waveguide section) were micro-transfer-printed to form the active region of the laser cavity using a 40 nm BCB bonding layer. Figure 19 shows an array of tunable lasers after postprocessing. The series resistance of the micro-transfer-printed SOAs is 15 Ω. A representative P-I curve obtained at 20 ○ C is shown in Fig. 20, which reveals a threshold of 70 mA and waveguide-coupled output power over 2 mW at a bias current of 110 mA. The abrupt changes in the output power are attributed to mode hops in the laser emission during bias current tuning, as is typical in a long laser cavity. This can be overcome by introducing a phase section in the laser cavity. A wide wavelength tuning over 48 nm is achieved by adjusting the thermal dissipation in the microheaters, as the recorded spectra in Fig. 21 illustrate.

VI. CONCLUSION
μTP is a powerful approach to integrate a variety of optoelectronic components, realized in dense arrays on a III-V source wafers, on SiPh target wafers. Devices include essential III-V SOAs, lasers, and photodiodes enabling advanced Si PICs. The technique is very well suited to massively parallel integration of these devices. In fact, nearly every material system/device that can be released from the substrate on which it was fabricated can be μTP. This creates opportunities for efficiently integrating other optical functions such as optical isolators, electro-optic modulators, and even electronic driver circuits (when realized on an SOI substrate) on the Si photonic platform. It can enable more complex PICs in nontelecom wavelength ranges such as the visible (VIS), near-infrared (NIR), and the mid-infrared (MIR), based on passive Si waveguide platforms such as SiN (VIS/NIR) and Ge-based (MIR) waveguide circuits and different III-V semiconductor technologies for light generation, modulation, and detection. The demonstrations presented in this paper are mostly based on the transfer printing of individual devices on target photonic dies. In order to introduce this technology to industry, wafer-level integration in a massively parallel way has to be investigated.

ACKNOWLEDGMENTS
This work was supported by the Methusalem funding of the Flemish Government, by the H2020 projects TOPHIT, TeraBoard and CALADAN, the ECSEL project MicroPrince, the INTERREG France-Wallonia-Flanders project SAFESIDE, and by the Irish Photonic Integration Centre.