Strain evolution of SiGe-on-insulator obtained by the Ge-condensation technique

Compressively strained SiGe-On-Insulator (SGOI) made by the Ge-condensation technique is used as a performance booster for ultrathin fully depleted silicon-on-insulator transistor technology. Here, we report on the evolution of the compressive strain in the SiGe film along the formation of local SGOI. For this, experimental maps of lattice strain with nanometer spatial resolution have been obtained by dark-field electron holography and compared to results from numerical models describing the mechanics of the structures. In particular, we report on unexpected strain evolutions when the top semiconductor layer is patterned to fabricate the shallow trench isolations that separate the Si nMOS from the SiGe pMOS areas. Dramatic and long-range relaxation of the compressive SiGe layers occurs, while no extended defects are formed in the crystal. The phenomenon involves relative horizontal displacements between the SiGe layer and the underlying Buried Oxide (BOX). We suggest that the Ge-enrichment of the layer close to this interface by the Ge-condensation technique modifies the SiGe/BOX interface and that strain relaxation results from the propagation of some interfacial defects from the edge to the center of the structure, driven by the shear stress at the interface.Compressively strained SiGe-On-Insulator (SGOI) made by the Ge-condensation technique is used as a performance booster for ultrathin fully depleted silicon-on-insulator transistor technology. Here, we report on the evolution of the compressive strain in the SiGe film along the formation of local SGOI. For this, experimental maps of lattice strain with nanometer spatial resolution have been obtained by dark-field electron holography and compared to results from numerical models describing the mechanics of the structures. In particular, we report on unexpected strain evolutions when the top semiconductor layer is patterned to fabricate the shallow trench isolations that separate the Si nMOS from the SiGe pMOS areas. Dramatic and long-range relaxation of the compressive SiGe layers occurs, while no extended defects are formed in the crystal. The phenomenon involves relative horizontal displacements between the SiGe layer and the underlying Buried Oxide (BOX). We suggest that the Ge-enrichment of the layer cl...

The engineering of the elastic strains in the channel of Complementary Metal-Oxide-Semiconductor (CMOS) transistors is being used to boost the performance of microelectronics devices. 1 Tensile strain increases electron mobility, while compression of the lattice improves hole mobility. 2 Different strategies have been adopted to manipulate locally the mechanical strain during the fabrication of transistors, such as the introduction of lattice mismatched strained sources and drains 3 and of stressed Contact Etch Stop Layers (CESL). 4 Alternatively, prestrained semiconductor substrates have been adopted, in particular in Fully Depleted Silicon-On-Insulator (FD-SOI) technology. 5 The co-integration of Si channels for nMOS and compressively strained SiGe channels for pMOS transistors is obtained through the local transformation of the top-Si layer into SiGe via the Ge-condensation technique. 6,7 The process starts with the epitaxy of a SiGe layer on top of the Si film from the Silicon-On-Insulator (SOI) areas designated for pMOS transistors. The oxidation of this SiGe layer consumes preferentially Si atoms, while Ge atoms are injected into the Si underlayer. 8 During this process, the initial Si layer is thus progressively enriched with Ge, while the resulting oxide can be removed at the end. A particularity of this process is that, when processing full wafers, the formed SiGe crystal keeps the same in-plane lattice parameter than the original Si. Hence, this layer is found under biaxial compressive strain and defines a compressive SiGe-On-Insulator (c-SGOI) structure. 9,10 In this work, we study the evolution of strain of initially compressive SiGe-On-Insulator layers fabricated using the Gecondensation technique along the fabrication route leading to the formation of high mobility channels for ultrathin FD-SOI p-type devices. For this, we have combined experimental lattice strain maps obtained using a sophisticate Transmission Electron Microscopy (TEM) technique providing nanometer spatial resolution and numerical models describing the mechanics of the structures. In particular, we report on some unexpected and dramatic strain evolutions of the SiGe layer when the top semiconductor layer is patterned to fabricate the Shallow Trench Isolations (STI) needed to electrically separate the p from the nMOS transistors. Indeed, long-range elastic relaxation of the c-SGOI is observed, which involves nonelastic relative horizontal displacements along APL Mater. 7, 041120 (2019); doi: 10.1063/1.5088441 7, 041120-1 ARTICLE scitation.org/journal/apm the interface between the SiGe layer and the underlying Buried Oxide (BOX). These results are discussed and enlighten the degradation of the mechanical properties of the SiGe/BOX interface formed by the Ge-condensation technique. Finally, a phenomenological relaxation mechanism is proposed. The investigated structures were fabricated in a state-of-the-art 300 mm technology semiconductor facility using SOI wafers with a 11 nm thick top-Si layer and a 20 nm thick BOX. Figure 1 summarizes the fabrication process of the samples, detailed as follows. The Ge-condensation process starts by masking the nMOS regions. In the foreseen pMOS regions, 8.5 nm of epitaxial Si 0.75 Ge 0.25 is epitaxially grown by Rapid Thermal Chemical Vapor Deposition (RT-CVD). A first oxidation process is carried out by Rapid Thermal Oxidation (RTO) at 1100 ○ C during 45 s to obtain a 13 nm thick SiGe layer with a Ge concentration varying linearly from 27 at. % at the top to 5 at. % at the interface with the BOX. 11 Sample A (depicted in Fig. 1) is taken at this step to obtain information on the strain distribution close to the vertical interface separating the original SOI (nMOS masked area) and the SGOI (pMOS area). The wafer is then furnace annealed under oxidizing atmosphere at 800 ○ C for 1h30, reducing further the thickness of the SiGe film down to 9 nm. This process causes a pileup of Ge to a concentration of 50 at. % below the oxide/SiGe interface. 11,12 For the fabrication of STI, a hard mask is deposited over the whole wafer. It consists of a 50 nm thick SiN layer deposited by Low Pressure CVD (LP-CVD) at 780 ○ C onto an ultrathin SiO 2 layer. The intrinsic stress of the SiN layer, measured by wafer bow on dedicated Si wafers, is of 1.2 GPa. 13 The mask is then opened at the edge of the SOI/SGOI interface, in the SOI region, and shallow trenches are fabricated by dry etching and filled with SiO 2 by Subatmospheric CVD (SA-CVD). Sample B (depicted in Fig. 1) is taken at this step to measure the strains in the SiGe layer, close to the STI edge. The fabrication goes on by annealing the wafers under N 2 at 1050 ○ C for 30 min to densify the STI oxide. The densification is expected to generate a tensile stress of the order of 130 MPa in the oxide. 14 This thermal budget also promotes Ge diffusion and leads to the homogenization of the Ge concentration across the SiGe layer at about 22 at. %. 11 After that, the SiN mask is removed by Chemical Mechanical Planarization (CMP) followed by selective chemical etching. Sample C is taken at this step and depicted in Fig. 1.
To image and map the strains in the structures, we have used Dark-Field Electron Holography (DFEH). 15 The experiments were performed on a Hitachi HF-3300 transmission electron microscope operating at 300 kV. The equipment is specifically designed for holography, 16 equipped with a cold-field emission source, an imaging aberration corrector (CEOS B-COR 17 ), a dedicated Lorentz mode position of the sample holder above the objective lens, a multiple biprism system, 18 and a 4k CCD camera. The holograms were recorded using ⟨220⟩ and ⟨004⟩ diffracted beams, 10 s exposure time, and 1.0 nm fringe spacing. Strain and rotation maps were reconstructed with a spatial resolution of 3 nm using HoloDark plugin 19 for DigitalMicrograph. All strain values are given relatively to the reference unstrained Si lattice from the substrate under the BOX. The SOI substrates we have studied show an initial miscut 20 (or tilt angle) of +0.4 ○ . In the conventions used here, layer rotation values smaller than the miscut define clockwise rotations. The TEM specimens were prepared by Focused Ion Beam (FIB) 21 using a dual-beam FEI Helios 600i.
Numerical models describing the mechanics of the structures, using the Finite Element Method (FEM), were built on COMSOL Multiphysics software with the structural mechanics module. The elastic constants of SiGe are obtained by combining the ones of Si and Ge 22 according to Vegard's law. The SiO 2 and SiN are described as isotropic materials of Young modulus of 70 GPa and 280 GPa and Poisson coefficients of 0.17 and 0.23, respectively. Above 960 ○ C, 23 the SiO 2 is modeled assuming a Maxwell viscoelastic behavior. 24 The lattice parameter of SiGe is obtained using the relation a SiGe (Å) = 5.431 + 0.20x Ge + 0.027x Ge 2 , x Ge being the atomic concentration of Ge. 25 For instance, Si 0.78 Ge 0.22 has a lattice difference of 0.83% relatively to relaxed Si. Hence, in our convention, a fully relaxed Si 0.78 Ge 0.22 is characterized by a strain value of +0.83% and a fully (compressively) strained SiGe is characterized by an in-plane strain εxx = 0%, i.e., when its in-plane lattice parameter is the same as the one associated with the relaxed Si reference. Samples to be observed by TEM are thinned by FIB down to about 90 nm. Thus, they suffer some elastic relaxation close to the two free surfaces. FEM is used to calculate the strain of the sample using 2D models in two extreme cases, assuming either a fully relaxed infinitely thin lamella ("plane stress" approximation, σ iy = 0 GPa with i = x, y, z; y being the thinning direction and z being the normal to the wafer surface) or a bulk sample ("plane strain" approximation, ε iy = 0 with i = x, y, z). 26 Strain values obtained from these two models never differ by more than 0.03%, i.e., below the precision of the DFEH measurement. For this reason, experimental DFEH mappings well reproduce the actual strain fields which reside in the structure before thinning. The sequence of fabrication steps is implemented by using the results of a model step as inputs for the subsequent one. In Fig. 2, we display the results we have obtained on sample A, i.e., after the Ge-condensation process, in the region where the Si and SiGe layers coexist and intersect. model predicts rather clockwise rotations of the layer at the STI edge.
It is important to note that this strain relaxation is not associated with the formation of any detectable extended defect in the SiGe crystal and thus cannot be associated with the plastic relaxation of this layer. To address this issue, we have modified our model. As the processes carried out after sample A involve only relatively low temperatures, some viscous behavior of the BOX is unlikely to have influenced the strain state of the SiGe layer. Instead, we suggest that the strain redistribution observed in sample B results from relative displacements between the SiGe and BOX materials, at the interface. 27,28 We have thus decoupled in the model the displacements between the two sides of the SiGe/BOX interface. A thin elastic layer boundary approach is used, where the two boundary planes of each material defining the interface are now linked by elastic forces of equal amplitudes but of opposite directions and proportional to the relative displacement they suffer at this point. It is introduced in the FEM model using the following expression: where σ is the stress of the thin elastic layer, k ⃗ t (respectively k ⃗ n ) is the tangential (respectively normal) stiffness constants per unit area of the thin elastic layer, and u + − u − describes the relative displacement of the materials between both sides of the interface. Main characteristics of the experimental results can be reproduced using this model we have named "FEM thin elastic interface". The agreement between experimental results and simulations can be rendered excellent, provided the tangential and normal stiffness constants per unit area of the thin elastic layer located at the SiGe/BOX interface are properly adjusted. Figures 3(c) and 3(g) show the results obtained with kt = 1 × 10 16 N m −3 and kn = 3 × 10 16 N m −3 . Moreover, this description of this interface can also simulate the rotation characteristics we have observed [ Fig. 3(h)]. Indeed, the tensile SiN layer deposited onto the compressive SiGe layer defines a bilayer structure which can now efficiently release stress by generating a clockwise rotation of the system from 25 nm to 200 nm from the STI edge. The FEM thin elastic interface model well reproduces the larger strain relaxation of the SiGe layer measured in the vicinity of the STI [ Fig. 3(d)]. Finally, it is interesting to note that this model predicts that the relaxation of the SiGe layer produces a horizontal displacement toward the STI trench with a maximum value of 0.8 nm at the STI edge.
Sample C is obtained after STI annealing at 1050 ○ C for 30 min, i.e., after the highest thermal budget the wafer has received, followed by CMP processing and SiN hard mask removal. It is important to remind that following this high temperature annealing, the SiGe composition is constant over the layer depth and equal to 22 at. %.
The experimental εxx map [ Fig. 4(a)] and the associated profile in Fig. 4(d) show that the Si 0.78 Ge 0.22 layer is fully relaxed close to the STI edge (εxx = 0.8%) and stays highly relaxed up to 300 nm from this edge (εxx is still 0.6%). The rotation map shown in Fig. 4(e) and the associated profile [ Fig. 4(h)] still show a large anticlockwise rotation of 1.2 ○ at the STI edge, an inversion to clockwise rotation at a distance of 70 nm from it and a slow return to the miscut angle of 0.4 ○ at larger distances. These experimental results evidence a further and significant strain relaxation of the SiGe layer following this last processing step. As shown in Figs. 4(b) and 4(f), the regular FEM model falls short on simulating this behavior. Although the viscous flow of the BOX (BOX creeping 29 ) was allowed in the model, the predicted elastic relaxation of the SiGe layer is by far underestimated. In the light of these comparisons, it becomes clear that, again, the experimental results cannot be explained without allowing large relative displacements along the SiGe/BOX interface. For this reason, we have used our FEM thin elastic interface model. Figure 4(c) and the corresponding profile in Fig. 4(d) show that excellent agreement between this model and the experimental results can be obtained by keeping the same normal interface stiffness constant kn = 3 × 10 16 N m −3 than previously used but further reducing the tangential interface stiffness constant down to kt = 2 × 10 15 N m −3 . In this case, the relaxation of the SiGe layer induces a horizontal displacement with a maximum value of 3.8 nm at the STI edge. This denotes a further degradation of the SiGe/BOX interface during this process step. Since we do not expect that the planarization itself, carried out at room temperature, may have affected the interface, we believe that this loosening of the SiGe/BOX interface properties must be put in relation with the Ge-enrichment of the SiGe layer at the interface (from 5 to 22 at. %) resulting from the high temperature annealing used to densify the STI oxide. The large relaxation of the SiGe layer we have evidenced after this step can now be understood as resulting from the removing of the tensile SiN hard mask. Indeed, this thick layer hosting a high elastic energy density (+0.13 J m −2 ) was maintaining the underneath SiGe layer (hosting itself an elastic energy density of −0.05 J m −2 ) under compressive stress.
Finally, we need to discuss some mechanism able to explain the SGOI film over-relaxation we have evidenced during the STI fabrication. We have seen that such relaxations typically involve horizontal displacements of several atomic bond lengths close to the STI edge. Thus, this behavior must rely on some nonelastic micromechanisms. Since the relaxations are observed in the vicinity of trenches, we infer that they result from the production of successive elementary relative horizontal displacements of the film over the SiGe/BOX interface, from the STI edge toward the center of the structure. Since we have not observed any delamination or cracking of this interface, we further infer that these relative displacements are produced by the propagation of some interfacial defects that allow the dynamic reconstruction of the interface. Indeed, following STI formation, some dramatic shear stress is generated at the very edge of the STI and is maximum at the SiGe/BOX interface. We suggest that the reduction in this shear stress provides the driving force for the nucleation and/or propagation of such defects. Initially maximum at the STI edge, the shear stress propagates along the interface as the film incrementally slips from the edge and thus decreases in intensity until it reaches a distance from the edge where the elastic shear energy is not sufficient to sustain the defect propagation mechanism. From this region inwards, the system again behaves elastically. Finally, within this scenario, the kt values needed in the model to simulate the experimental results only reflect the intensity of the interfacial shear stress needed to propagate the defect responsible for relaxation along the interface. The ability of this interface to sustain more or less easily such a mechanism for stress relaxation must be related to the evolution of the SiGe layer composition and structure during Ge-enrichment and diffusion. As kt decreases when the Ge concentration at the interface increases, we suggest that the SiGe/BOX interface is somehow modified by the continuous arrival of Ge atoms, during the Ge-enrichment and homogenization steps, both processes occurring at high temperature.
In summary, we have studied the evolution of strain in c-SGOI layers fabricated locally onto SOI wafers by the Ge-condensation technique. We show that, at first, BOX creeping, i.e., the viscous flow of SiO 2 at high temperature, allows the redistribution of strain in the vicinity of the vertical interface separating the Si from the SiGe top layers. Furthermore, when the STI trench is etched between the two layers, the initially compressive SiGe layer anomalously relaxes by allowing some relative displacement between the SiGe layer and the BOX in the interface plane. The structure first reacts to the stress exerted by the tensile SiN hard mask but relaxes over long distances when this mask is removed. We have also noticed that this degradation of the mechanical properties of the SiGe/BOX interface increases as the concentration of Ge in the region close to this interface increases, at least when activate through diffusion at high temperature.
We have proposed a mechanism where the relative displacements of the SiGe layer and the BOX are rendered possible by the propagation of defects at the interface. These defects, which APL Mater. 7, 041120 (2019); doi: 10.1063/1.5088441 7, 041120-5 ARTICLE scitation.org/journal/apm probably nucleate close to the STI edge where the shear stress is maximum, further propagate from the edge to center of the structure, in the opposite direction to the displacements of the SiGe layer, driven by the shear stress. The nature and microscopic structure of this defect cannot be elucidated from our studies and thus remains elusive. However, the Ge-enrichment technique used to transform the top-Si layer into a SiGe layer is pointed out to generate the modifications of the structure of the interface at the origin of the mechanical degradations we have evidenced.