A capacitance spectroscopy-based platform for realizing gate-defined electronic lattices

electronic lattices T. Hensgens, a) U. Mukhopadhyay, a) P. Barthelemy, a) R. F. L. Vermeulen, R. N. Schouten, S. Fallahi, G.C. Gardner, C. Reichl, W. Wegscheider, M. J. Manfra, and L. M. K. Vandersypen b) QuTech and Kavli Institute of Nanoscience, Delft University of Technology, 2600 GA Delft, The Netherlands Department of Physics and Astronomy, and Station Q Purdue, Purdue University, West Lafayette, Indiana 47907, USA Solid State Physics Laboratory, ETH Zürich, 8093 Zürich, Switzerland


I. INTRODUCTION
Artificial lattice structures have the potential for realizing a host of distinct quantum phases 1 . Of these, the inherent length scale of optical platforms allows for a clean emulation of quantum mechanical band physics, but also means interactions are weak and going beyond a single-particle picture is difficult 2,3 . For electronic implementations in solid-state, interactions can be made non-perturbatively strong, potentially leading to a host of emergent phenomena. An example is shown in graphene superlattices, where not only Hofstadters butterfly physics 4-7 but also interaction-driven and emergent fractional quantum Hall states in the butterfly appear 8 . The ideal platform would host a designer lattice with tunable electron density and lattice strength, allowing to emulate band physics for a wide variety of lattice types and giving access to the strong-interaction limit of correlated Mott phases [9][10][11][12][13] . Semiconductor heterostructures with nano-fabricated gate structures provide this flexibility in lattice design and operation, yet inherent disorder in the host materials as well as the short length scales required make the realization of clean lattices difficult [14][15][16] .
In this Letter, we introduce a novel experimental platform for realizing artificial gate-induced lattices in semiconductors, based on a capacitance spectroscopy technique [17][18][19] , with the potential to observe both singleparticle band structure physics such as Hofstadter's butterfly and many-body physics such as the interaction driven Mott insulator transition. We discuss different gating strategies for imprinting a two-dimensional periodic potential at length scales where interactions are exa) These authors contributed equally to this work b) Correspondence should be sent to l.m.k.vandersypen@tudelft.nl pected to be strong, characterize intrinsic disorder levels and show first measurements of double gate devices.

II. HETEROSTRUCTURE AND CAPACITANCE SPECTROSCOPY
To host the 2D electron gas (2DEG), we use a GaAs quantum well with AlGaAs barriers, grown by molecular beam epitaxy. The substrate contains a highly Si-doped GaAs layer that acts as a back gate. It is tunnel coupled to the 2DEG through a Al x Ga 1−x As tunnel barrier (see Fig. 1a and Table I). There is no doping layer above the quantum well in order to avoid an important source of disorder. A metallic top gate is fabricated on the surface. A variable capacitor forms between the back and top gates: when an alternating potential difference is applied between them, electrons tunnel back and forth between the back gate and the 2DEG, modifying the capacitance by an amount proportional to the density of states (DOS) of the 2DEG. The tunnel frequency depends mainly on the thickness and the Al content (x) of the tunnel barrier. At the limits of zero or infinite DOS, the system behaves like a simple parallel plate capacitor, described by the distance between top gate and back gate or top gate and 2DEG, respectively. The capacitance is read out using a bridge design with a reference capacitor 20 , where the voltage at the bridge point is kept constant (Fig. 1b) by changing the amplitude ratio and phase difference of AC signals applied to each capacitor (see supplementary material section A for experimental details).
To impose a periodic potential in the 2DEG, we pattern a metallic gate into a grid shape before making the top gate. From a capacitance spectroscopy perspective, this double-gate structure can be made with two differ-ent designs. In the first design, the top gate is separated from the grid gate by a thick dielectric layer, rendering its capacitance to the grid gate negligible (a few pF compared to tens of pF). In that case, we can ignore the grid gate from an AC perspective altogether (Fig. 1c). Alternatively, we can minimize the separation between the two gate layers, such that the capacitance between the two top gates (100's of pF) exceeds the sample capacitance. Here the two gates effectively form a single gate (Fig. 1d), as seen in AC. We investigate both designs below, starting with describing the fabrication (limits) and following with measurements of disorder levels and imposed potentials.

III. GATE DESIGN AND FABRICATION
We distinguish devices with a single global gate (Fig. 1a) and devices with two layers of gates: a grid gate and a uniform global gate on top (Fig. 1c-d). The former will be used to characterize disorder levels in the next section, whereas the latter allows for the imposition of a periodic potential. The strength of the imparted periodic potential depends on the dielectric choice (thick or thin, compare Fig. 1c,d), gate design, grid gate pitch and the maximum voltages that can be applied. Grid gates are made with a pitch of 100 -200 nm ( Fig. 2a-b), which is mainly limited by the fabrication constraints.
The maximum voltage is determined by the onset of leakage through the heterostructure or the accumulation of charges in the capping layer, and thus depends on heterostructure details such as the Al concentration and layer thicknesses.
The expected imparted potentials at the 2DEG with typical maximum voltages for both designs are shown in Fig. 2(c-f) (calculated using COMSOL electrostatic simulation software). In order to observe a Mott transition and the corresponding localization of electrons on individual sites, the periodic potential amplitude must exceed the local Coulomb repulsion (typically several meVs) 21 . For 200 nm grids, both designs show similar maximum effective periodic potentials, and they should suffice for the formation of quantum dots. For the 100 nm grids, however, the achievable potentials exceed the charging energy only when using the overlapping gate design. For the smaller pitch grid, effective shielding of the top gate voltage by the grid gate is larger when the top gate is farther away from the heterostructure. Therefore, an overlapping gate design is required to go to sufficiently strong periodic potentials for localization at 100 nm siteto-site pitch.
Furthermore, we note that screening induced by mobile charges in the back gate region has both desired and undesirable consequences. An intended benefit is that disorder from charged impurities or defects in the heterostructure is partly screened, and the more so the closer to the back gate the impurities or defects are located 13 . However, electron-electron interactions and the gate-voltage imposed potential modulation itself are partly screened as well, and more so as the lattice dimension is reduced.
Double gate devices with either a thick (Fig. 1c) or a thin dielectric (Fig. 1d) between the two gates require different fabrication processes. Here we discuss the fabrication of the active regions in both designs, which have a size of 200 µm by 200 µm. The detailed information for all steps in the fabrication is provided in the supplementary material section B. In both designs, the square grid metallic gates are fabricated at pitches of 100-200 nm using electron beam lithography and evaporation of metals in a standard lift-off process ( Fig. 2a-b). In the first design, both gates are made of Ti/Au(Pd) and separated by > 200 nm layer of oxide, such as plasma-enhanced chemical vapor deposition grown SiO x or plasma-enhanced atomic layer deposition grown AlO x . In the second design, both gates are made of Al, and an oxygen (remote) plasma oxidation step is used after depositing the first Al layer to ensure sufficient electrical isolation between the two layers by transforming part of the Al gate to Aluminum oxide 22 . In this design, we measure resistances exceeding 1 GΩ over several V.
Because of the fabrication process, there are limits in the periodicity and homogeneity of the grid gate layer. We typically find (1) that plaquettes of smaller size than 40 nm x 40 nm will not lift off and that (2) the grain size of a particular metal determines the narrowest lines that can be made reliably with liftoff. For the materials used here, AuPd and Al, these effects limit the minimum lattice pitch (Fig. 3a). Furthermore, we have analyzed the homogeneity of the lattices by using image processing techniques to give the statistics of the nonmetal plaquette areas (Fig. 3b). A more relaxed lattice constant means higher relative homogeneity but this is not necessarily helpful: it also increases the flux through a single plaquette when a perpendicular magnetic field is applied (relevant for Hofstadter butterfly physics, as will be described below) and it decreases the charging energy, relevant for Mott interaction physics.

IV. MEASUREMENTS
A. Global gates: disorder levels In order to assess disorder levels, we first measure the devices with a single uniform top gate. We measure the capacitance at frequencies below and above the rate at which electrons tunnel between the 2DEG and the doped back gate region as a function of bias voltage ( Fig. 4a-b) and magnetic field. Having measured the capacitance at low and high frequencies, we calculate the equilibrium DOS. There are essentially two unknown parameters in this conversion, namely the distance from top to bottom gate and the relative location of the 2DEG itself. The former can be directly inferred from the capacitance at high frequency, the latter by using either the known effective mass or the Landau level splitting with magnetic field as benchmarks (see supplementary material section C for details on this conversion). As a magnetic field is turned on, we see the onset of Landau level formation. For magnetic fields above 2 T, we observe a splitting between the spin subbands of the Landau levels which increases with the applied magnetic field (Fig. 4c). For a given magnetic field, the separation between the two subbands of any Landau level is significantly larger than the Zeeman energy with g = -0.44 for bulk electrons in GaAs 17 . This enhanced Zeeman splitting is an effect of the Coulomb repulsion between electrons in the same subband 23 .
We focus on the low-field data ( Fig. 4d) and infer disorder levels from the density of states data (Fig. 4e). Gaussian fits to the Landau levels yield typical widths ranging between 0.4-1 meV at densities above 10 11 cm −2 , which, although hard to compare directly to the mobilities reported for transport-based wafers [14][15][16] , is comparable to previously reported values for similar heterostructures 24 . The Landau levels themselves (aliased at low fields in Fig. 4d) become visible above fields of roughly 0.25 T, corresponding to densities per Landau level of 1.2×10 10 cm −2 and cyclotron gaps of 0.43 meV. The Landau level width did not change when we increased the mixing chamber temperature from 10 mK to 100 mK or when we varied the excitation voltage. Furthermore, the Landau level width was consistent across fabrication schemes, but did vary with the wafer used. Therefore, we consider it a heuristic metric for the achievable disorder levels on a particular wafer.
We have tried to optimize wafer design to minimize this disorder, whilst allowing for the imposition of a periodic potential. All in all, over twenty different GaAs/Al x Ga 1−x As wafers grown by molecular beam epitaxy have been used. Growth details of the wafers can be found in Table I.
The initial wafer (W1) design was based on Dial et. al. 25 , and was grown on a conducting substrate. This simplifies the fabrication of single-gate devices, as an unpatterned ohmic back gate contact can be directly evaporated on the back side of the wafer, while simple metallic pads fabricated on the front side can be directly bonded to and used as a top gate. A double-gate design requires dedicated bond pads, which would give a sizable contribution to the total capacitance when fabricated directly on the wafer. The device used for Fig. 5a-b in the main text, fabricated on one of the first rounds of wafers (W2), therefore, had bond pads on top of the thick dielectric separating the two gates. This strategy is not compatible with the second design, where there is no thick dielectric layer, and also gives a very low wire bonding yield due to poor adhesion of the dielectric layers on the GaAs surface. Furthermore, handling both sides of a substrate during fabrication risks contaminating the front surface, and is particularly suboptimal when detailed features (grid gates) are present as well. Subsequent wafers were therefore grown with a 400-800 nm thin degenerately Si doped back gate region that is contacted from the front side of the wafer, and is etched to form electrically isolated device and bond pad mesas. We have further tried to optimize the wafer stacks aiming to increase the amplitude of the periodic potential at the 2DEG and to decrease disorder levels. A stronger periodic potential can be obtained by either increasing the maximum possible gate voltage, reducing the separation between the grid gate and the 2DEG or increasing the distance between the 2DEG and the back gate. The latter may also reduce disorder caused by dopant diffusion from the back gate. Increasing the quantum well thickness is also expected to reduce the effect of disorder by accommodating more of the electron wave-function away from the interfaces. Concretely, we have first varied spacer layer thickness (25 and 35 nm) and quantum well widths (15 and 30 nm). In further attempts to optimize the trade-off between the periodic potential that can be set at a fixed voltage and the maximum voltage we can apply to the gates before leakage sets in, we varied the blocking barrier thickness (40, 50, 60 and 70 nm) and fabricated devices with a thin dielectric layer (see wafers M1 and W3) added underneath the grid gate. None of these, however, managed to noticeably increase the maximum potential we could impose on the 2DEG, or to decrease disorder levels. The strongest effect on disorder was obtained by changing the aluminum concentration in the Al x Ga 1−x As blocking and tunnel barrier (from x = 0.31 everywhere to x = 0.36 in the blocking barrier and x = 0.20 in the tunnel barrier), while slightly increasing the tunnel barrier thickness in order to keep the tunnel rates roughly the same (see Table I). The measurements shown in Fig. 4  For measurements of two-layer gate devices of both designs (Fig. 5), we keep the grid gate potential fixed, given that it serves as the gate voltage of the first transistor in the amplification chain, and map out the remaining two gate voltages over as large a range as possible. Initial devices of both designs indeed show accumulation as a function of the two gate voltages (transition from light grey to blue in Figs. 5a,c). At voltages where we expect a flat periodic potential (close to the center of each panel in Fig. 5), and for our final set of devices, we can still distinguish well-defined Landau levels, indicating that the added fabrication steps themselves do not severely increase the disorder levels (data not shown). This disorder in the potential landscape also leads to a broadening of the onset of accumulation, seen in the center of Figs. 5a,c.
For devices of the first design, this broadening increases as we move away from the center, along the grey-blue boundary (Fig. 5a). This suggests that we see a gatevoltage induced spatial variation in the 2DEG potential that exceeds disorder levels (0.4-1 meV) at low densities. Based on electrostatic simulations of the strength of the imposed potential, the gate-voltage induced variation is indeed expected to exceed the disorder levels (Fig. 2). The asymmetry between positive and negative top gate values seen in the data could possibly be explained by effective disorder levels being smaller when charges accumulate mainly underneath the grid gate, as compared to when charges accumulate mainly underneath the dielectric. Finally, in Fig. 5b we resolve separate lines at the onset of accumulation for negative top gate voltages. Even though we expect to see evidence of miniband formation, we do not attribute these splittings to miniband formation, as they show a much larger periodicity in back gate voltage than the 6 mV expected from the density of states calculation (see below).
For devices of the second design, the widening of the onset of accumulation is less pronounced , but the effect of gating is seen at finite magnetic fields, where a voltage difference between the grid and top gate effectively blurs out the gaps between Landau levels (Fig. 5c-d). This indicates that the imposed local potential variation must be comparable to or stronger than the Landau level spacing at 1 T (1.7 meV). We conclude that also for the second design, the 200 nm periodic potential exceeds disorder levels.
Increasing further the amplitude of the potential variation induced by the gates was limited by saturation of the gating effect. For the first gate design, we find a saturation to the effect of the top gate in gating the 2DEG at gate voltages exceeding 35 V in absolute value. This could be a sign of charges building up at interface of the capping layer and the dielectric, or in the dielectric itself, which screen the effect of the top gate. This saturation limits the potential we can impose on the 2DEG. For the second gate design, a maximum voltage difference of roughly 2 V can be set between the back gate and the surface gates before leakage starts to occur. As an attempt to allow for larger gate voltages before leakage through the heterostructure occurs, we have tried the same fabrication but with an additional 5 nm ALDgrown AlO x dielectric placed underneath the grid gate. This indeed prevents leakage but the gating effect saturated at the same voltages as where leakage occurred for devices without this additional dielectric. Therefore, 2 V was still the maximum voltage we could apply between the back and surface gates in the second design.

V. DISCUSSION: WHAT TO SEARCH FOR IN FUTURE DATA
As we have just seen, (i) the periodic potential exceeds disorder levels. In order to see Hofstadter's butterfly and Mott physics, however, we also need to (ii) be able to resolve the induced density of states modulations and (iii) the lattice potential from the grid itself should be sufficiently homogeneous. The latter two considerations will be discussed below, based on the data presented.
Using either gate design we find both gates to influence the accumulation of charges in the quantum well as expected, but neither shows clear evidence of a lattice potential imposed on the 2DEG (Fig. 5). At zero magnetic field, a lattice potential would lead to minibands that manifest as periodic modulations in the density of states (and capacitance) with a period corresponding to two electrons per lattice site, or 5×10 9 cm −2 for a 200 nm square grid. Expressed in mV on the back gate, this corresponds to a period of 6 mV. Furthermore at finite magnetic field, Landau levels are expected to show structure due to Hofstadter butterfly physics 15,26 , with the largest gaps expected around k ± 1/4 of a flux quantum Φ 0 threading each lattice plaquette (with k an integer; Φ 0 corresponds to 104 mT for a 200 nm grid). Finally, a strong enough periodic potential would allow interaction effects to dominate. Miniband gaps are expected to split as filling starts to occur with a period of one electron per lattice site, akin to the interaction-driven Mott transition 11 . None of these effects are visible in Fig. 5 nor in many detailed targeted scans of magnetic field and gate voltages on devices with 200 and 100 nm grid gate periodicity.
If we compare the 5×10 9 cm −2 density modulations expected from miniband formation with the 1.2×10 10 cm −2 broadening of low-field Landau levels (global gate devices at high densities, i.e. we do not have evidence that we can resolve density variations below 1.2×10 10 cm −2 ), it is reasonable that gaps are not yet seen opening up at densities corresponding to the filling of (pairs of) electrons on each lattice site. This suggests that either lattice size or wafer disorder has to be further reduced. As it proves hard to lift off plaquettes of metal that are smaller than roughly 40 nm by 40 nm, there is not much room to reduce lattice dimension further in this particular fabrication scheme (Fig. 3a). For 100 nm pitch grids, the period of the density modulations is expected to be four times larger, but is still comparable to current best-case scenario Landau level broadening. As such, reducing intrinsic disorder seems necessary. An appropriate goal would be to make double layer gate devices with Landau levels that are distinguishable at fields below 100 mT.
The visibility of Hofstadter butterfly gaps depends not only on the intrinsic disorder in the device, but also on the inhomogeneity in the plaquette sizes, as this would entail a different number of flux quanta threading through different plaquettes. If the size variations from electron micrographs of our devices translated to identical size variations in the periodic potential (Fig. 3b), we should just be able to distinguish the largest gaps 15 . It is hard to assess, however, whether this indicator from the electron micrographs directly correlates to the relevant physics in the 2DEG.

VI. OUTLOOK
There is room for further optimization of these devices. On the heterostructure side, the distance between the back gate and the 2DEG can be further increased, compensating with a decreased Al content in the tunnel barrier to keep the tunnel rate fixed. Furthermore, part of the spacer layer can be grown at reduced temperatures, which has been shown to strongly reduce disorder by limiting the diffusing of Si dopants from the back gate region 24 . On the fabrication side, there is still room left for a modest reduction of the lattice periodicity with the current lift-off process. Even smaller length scales can be obtained by switching to dry etching of the grid pattern, albeit at an unknown impact to wafer disorder levels.
In summary, we have demonstrated a novel platform intended for the realization of artificial lattices of interacting particles. Although fine tuning the design to the point where a sufficiently homogeneous and strong periodic potential can be applied remains to be done, the quantum Hall data already shows how the stronginteraction, low-temperature limit can be reached. Such a platform has potential for studying the interactiondriven Mott insulator transition 11,27 and Hofstadter butterfly physics 4 with finite interactions, and can be ex-tended from the steady-state measurements presented here to include time-domain measurements of excited states 25 .
The capacitance bridge is built on a printed circuit board (PCB) that is mounted on the 10 mK mixing chamber stage of a dilution fridge and whose main components are the device, the reference capacitor and a high electron mobility transistor (HEMT, that serves as the first amplifier). By mounting the HEMT orthogonal to the PCB surface, we can apply magnetic fields to the sample without influencing the amplification chain. All D/C lines on the sample PCB have R/C filters on top of the filtering in the fridge. A 10 and 40 MΩ resistance is used to bias the bridge point and top gate in D/C, respectively, and a bias-tee is added to bias the back gate on top of the measurement signal. The high frequency lines are not attenuated in the fridge, as we found this to lead to ground loop issues, but are instead attenuated on the PCB itself. Measurement excitations are simple sinusoidal signals that get attenuated to the V level and are generated using a signal generator at room temperature. The bridge point voltage is amplified further at 0.7 K and at room temperature and measured using a lock-in.
An iterative scheme is implemented to minimize the bridge point voltage by updating the amplitude ratio and phase difference of the two excitations as gate voltages and applied magnetic field are changed. The excitation on the sample side is kept constant and the excitation on the reference capacitor side is updated based on the secant method. For this, we model the bridge as a linear system of complex variables: Y = AX + B, where X is the reference signal, Y is the output from the lock-in, and A and B are complex numbers. Given two iterations with reference signals X i and X i+1 and respective output values Y i and Y i+1 , A and B are calculated as well as X i+2 = −B/A, which is subsequently set and Y i+2 measured. As the first two iterations, we take the last set reference signal as well as a point with a typically 1 % higher amplitude and a tenth of a degree increased phase. Convergence is reached when the amplitude dif-ference between the last two reference signals drops below some pre-defined value, typically chosen to be several parts per thousand of the amplitude itself. The sample capacitance C sample follows from the reference capacitor value C ref and the applied amplitude ratio R = V ref V sample and phase difference δφ = π + φ ref − φ sample at equilibrium: C sample = cos(δφ)RC ref .

B. Design and fabrication details
As discussed earlier, several different designs and fabrication recipes were used throughout this work to fabricate devices. In the first part, we give some general information on steps that have been employed for many of these fabrication runs. Next we describe fabrication processes of different dielectrics used in the first design to separate the top and grid gate layers. Finally, we provide detailed information for a fabrication run of the second design with overlapping aluminum gates, which serves as a clear example from which the steps required for fabricating the other devices measured can be deduced. All lithography steps were performed using electron beam lithography (Vistec EBPG 5000+ or 5200) at 100kV acceleration voltage. Etching Al x Ga 1−x As was done using diluted Piranha (1:8:240 H 2 SO 4 :H 2 O 2 :H 2 O) yielding etch rates of roughly 4 nm/s. The actual etch rate decreases on a timescale of minutes as the H 2 O 2 concentration slowly decreases. Spinning is done at 500 rpm for 5 seconds and then for 55 seconds at speeds listed below. Etching SiO 2 and AlO x was done using buffered HF (BOE 1:10) solutions. After either type of wet etch, devices are rinsed repeatedly in H 2 O. Adhesion issues for resists with HF etch times longer than 20 s mean iterative etching and re-baking is necessary. For the 366 nm AlO x layers, this meant we had to use a dry Cl etch to etch the bulk of the depth of the vias before finishing with a wet etch. Metallic layers were deposited using electron-beam evaporation at room temperature and subsequent lift-off in a solvent. The first design, with a thick dielectric separating the two gate layers, has been fabricated with two different dielectrics. For the results of Fig. 5a-b in the main text, plasma-enhanced chemical vapor deposition (PECVD) of 360 nm of SiO 2 as dielectric was used, which was found to introduce phase-noise during capacitance-bridge measurements. We have also fabricated devices with 366 nm of plasma-enhanced atomic layer deposition (ALD) grown AlO x dielectric (optical image in Fig. S 1a). Although these devices had less phase-noise, they showed large top gate hysteresis, rendering them practically impossible to measure with (Fig. S 1b). Furthermore, etching small vias through such a thick layer of alumina is very cumbersome. All devices of the first design had low yield in wire-bonding because of poor adhesion of the dielectric layers to the GaAs surface.
An overview of the fabrication steps for realizing double-layer gate devices with aluminum gates (second ii design) is given below. See • Bridges -spin PMMA 495K A8 resist at 6000 rpm -bake 15 min at 175 • C (400 nm) -lithography -cross-link PMMA strips through electron beam overdose at 25 mC/cm 2 . These sections act as bridges over which the leads will connect sample mesa and bond pad regions.
• Connection pads and markers -spin PMMA 495K A8 resist at 6000 rpm -bake 15 min at 175 • C (400 nm) -lithography -development 60 s in 1:3 MIBK/IPA -evaporation of 10/50 nm Ti/Au -liftoff in acetone and IPA rinse. These sections act either as markers or as pads that will be contacted on the top both by the Al gates and the leads contacting the bond pads. We found these thin layers of metal to be the most robust way to make an electrical connection (typically several Ohm) between the Al gates and the Au bond pads. -evaporation of 20 nm Al -lift-off in NMP at 70 • C using soft ultrasound excitation for 4 hrs and subsequent acetone and IPA rinse -oxidation in 20 min at 200 • C at 100 mTorr and 300 W RF power using the remote plasma of an ALD machine. We have optimized the lithographic sequential writing such that a 200 µm x 200 µm grid is written in one go and at under a minute, avoiding stitching errors and reducing the effect of drift (typically several tens of nm/min). We have done this by direct programming of an iterative sequence that the e-beam follows in writing the grid instead of the standard procedure of converting a design file (in this case a large square grid) to an e-beam lithography file using BEAMER software. Furthermore, we add a 200 nm thin frame around the grids whose overdose is chosen to counter proximity edge effects iii (Fig. S 2d). Note also that we found the conflicting requirements of high resolution and undercut required for lift-off to be best served using a single layer CSAR62 resist. Finally, we find feature size, yield and reproducibility to be limited by the grain size of the evaporated Al, instead of by the resist mask or lithography process. To achieve a smaller grain size, we used a fast Al evaporation rate of 0.2 nm/s. As such, Ti/Au but especially Ti/AuPd gates are easier to fabricate than Al gates but they cannot be oxidized and would require actual deposition of a dielectric. Also note that the lift-off based fabrication of grids allows for different lattice types to be made, see

C. Conversion from capacitance to density of states
In calculating density of states from capacitance data, we follow a procedure described before 17 . We model the system as a parallel plate capacitor made up of the top and bottom gates, with the potential for added charges at the location of the quantum well, as sketched in Fig. S 3. As a start, C high/low are measured as function of gate voltages and magnetic field values (Fig. S 4a). Note that the heterostructure stack is designed to keep the tunnel frequency in the middle of the experimental measurement window ( Fig. 4a-b in the main text): below 1 kHz signal to noise ratio declines (mainly because of the 1/f noise of the first transistor in the amplification chain) and above 2 MHz systematic errors occur (we find asymmetric crosstalk between the two excitation signals and the second transistor in the amplification chain).
The total voltage difference over the device is a combination of the electric fields V = V back − V top = E 1 (w + d) + E 2 d, which in turn depends on the charges on the plates as V = σtop(w+d) + σQWd . The total capacitance, which is the one measured at low enough frequencies, is defined as ∂σQW ∂V + small terms that depend on changing distances and which we ignore. The first term describes the bare capacitor, and is therefore equal to the total capacitance measured at high frequencies: C high = A w+d . The second term is the one of interest. It describes changes between the capacitance measured at low and high frequency because of the addition of charges in the quantum well, which allows us to infer changes in electron density using ∂n ∂V = − 1 e ∂σQW ∂V = 1 eA w+d d (C low − C high ) (Fig. S 4b). Figure S 3. Schematic representation of the device as a parallel place capacitor of distance w +d with an inserted quantum well at a distance d from the back gate. When the DOS at the quantum well is nonzero, charges can build up.
The voltage required to change the Fermi level E F of the quantum well can be found using a similar deduction to the one described above, and is described by a voltage-dependent lever arm α ≡ −e ∂V ∂EF . We find the lever arm by following the dependence of the Fermi level in the quantum well through changes in the electric field as ∂EF ∂V = −ew ∂E1 ∂V = −e w w+d + e wd w+d ∂n ∂V (Fig. S 4c). The first term describes how the Fermi level of a gapped system in the quantum well (δn = 0) changes with bias as expected given its relative location w w+d between the plates of a simple parallel plate capacitor (Fig. S 4c). It is the second term that encompasses the electron filling, showing the lever arm to increase when charges can be added to the quantum well (after accumulation this becomes the dominant term, see Fig. S 4b). Given the above expressions for density and Fermi level changes as function of gate voltage, we can define the density of states in the 2DEG through DOS = ∂n ∂V ∂V ∂EF = 1 e 2 A w+d d α (C low − C high ) (Fig. S 4d). As indicated by changes in C high in Fig. S 4a, the distances describing the system are non-static with gate voltage. In the case of (w + d), this is most likely due to back gate charges populating part of the spacer layer as the electric fields bend the conduction band edge, indeed increasing C high for more negative back gate voltages. The exact location of the charges in the quantum well and related distance d, however, we cannot directly infer from an independent measurement. As a first guess, the growth distances combined with the (w + d) extracted from C high suffices. A better estimate can be made using the known linear degeneracy of Landau levels with magnetic field, n LL = 2eB h (Fig. S 4b). To obtain the best possible calibration, however, we compensate for any further dependence of the relative quantum well position on back gate voltage by pegging the 0 T DOS after accumulation to the expected value of m π 2 ≈ 2.8 × 10 13 eV −1 cm −2 (Fig. S 4d), and use this calibration for nonzero magnetic field values. , both below and above the tunnel frequency. Top gate is kept constant for all measurements as it is serves as the bridge point, which is also directly contacted to the gate of the first transistor in the amplification chain. (b) Density as function of back gate bias. As the system becomes more gapped between Landau levels at higher fields, steps start to form in the graph that indicate the filling of distinct levels at well-defined densities.
(c) Lever arm as function of back gate bias. Note that the quantum capacitance of a large density of states in the 2DEG increases the voltage required to change the Fermi level, as expected. At zero density of states, however, the lever arm is simply the geometric ratio expected from the relative location of the quantum well between the top and bottom gate. (d) Density of states as function of the Fermi energy, which is the integrated lever arm. We choose zero in energy to lie close to accumulation.