Bending induced electrical response variations in ultra-thin flexible chips and device modeling

Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.

The last decade has witnessed tremendous advances in flexible and conformable electronics.Many applications have benefited and numerous new applications will arise from electronics that can bend and conform to threedimensional curvilinear shapes.][3][4][5][6][7][8][9][10][11] As for any new technology, the electronics over bendable substrates has its own share of challenges, a few of which (e.g., related to fabrication over large areas and integration on diverse flexible substrates 12 ) have already received significant attention.With the field advancing towards circuits and systems, the new set of challenges that require attention are related to reliable and uniform operation of flexible integrated circuits (ICs) under various bending states.Numerous parameters such as the crystal structure of the electronic substrate, the design of devices and circuits and their layout with respect to various crystal axes, and the energy band structure are affected by bending induced stresses and strains through variations in electrical parameters such as charge carrier mobility and threshold voltage.The bending induced effects can bring significant deviation in the response of flexible electronics from their designed values and may influence their effective use in the target application.Therefore, it is critical to understand the behavior of devices and circuits under different bending conditions and the interplay between mechanics, solid-state physics, and electrical and electronic inputs.A few articles have reported some of the stress-induced effects, 13 but the modelling of such variations, for example, to enable future computer aided design (CAD) tools, has not been reviewed so far.This paper will fill this gap by using studies related to electronic devices on ultra-thin chips (UTCs) made from silicon (Si).The goals of this survey paper are to: (1) review various types of bending and related induced stresses experienced by the UTCs and their analytical relationships.Various deformation types, modes of stresses (static and dynamic), surface orientations, device channel directions, and gate electric fields are considered.While the primary focus is on the bending-induced stress, the fabrication process-induced effects are also discussed for the sake of completeness; (2) review the impact of different types of stresses on the DC behavior of electronic devices and gain insights into energy band structure and transport properties; (3) correlate the bending induced stress with the variations in the output of devices and circuits; and (4) advance CAD tools by presenting new compact models.The proposed device models follow the comprehensive studies based on changes in the electrical parameters of strained transistors.The challenges in circuit simulation and implementation have been identified.As flexible electronic systems are often unconstrained during bending, the terms stress and strain are used interchangeably throughout this paper.
A visual summary of this paper is given in Fig. 1.The paper is organized as follows: Sec.II presents a historical perspective of the field.The mechanical aspects of various types of bending, including uniaxial, biaxial, and torsional deformations, experienced by UTCs are presented in Sec.III.Section IV describes the electrical behavior of Si resistors and transistors during bending and the effect of bendinginduced stress on electrical parameters of devices on UTCs.A survey of compact modeling of stress effects on complementary metal-oxide-semiconductor (CMOS) is given in Sec.V followed by a detailed analysis of the stress effects at the circuit-level given in Sec.VI.Finally, outlook and concluding remarks are put forward in Sec.VII.

II. HISTORICAL PERSPECTIVE
From the historical perspective, the field of flexible electronics has grown exponentially as evidenced by the trend in Fig. 2, which is based on the number of publications in this FIG. 1. Graphical overview of this review.FIG. 2. Plots showing publications since 1991 in the field of flexible electronics (y-axis on the right side), piezoresistive effects in all types of devices, i.e., planar as well and non-planar (y-axis on left side), modeling of devices responses in all types of devices after considering the piezoresistive effect (y-axis on the left side), and the modeling of device responses in all flexible electronic devices after considering the piezorsistive effect (y-axis on the left side).The data were extracted from Web of Science by searching keywords such as flexible electronics and modelling.
field since the early 1990s.The stress/strain or the piezoresistive effect related modeling of the response of devices based on various semiconducting materials also has a similar trend over the same period.However, until about 2005 the piezoresistive effect related studies were mainly based on electronics on planar and non-flexible substrates and they were carried out for different motivations-ranging from optimization of the fabrication process to enhancing the performance.5][16][17][18][19][20][21][22] A few review articles have covered aspects such as uniaxial and biaxial strain on carrier mobility in MOSFETs, [23][24][25][26] with a theoretical analysis of the physics of strained MOSFETs for different wafer surface orientations, channel directions, gate electric fields, and materials. 23,24,26These studies have positive implications for similar investigations in bendable or flexible electronics.For example, they tell us that the mechanical stresses are not always detrimental, as conventionally considered.8][29][30][31][32] In fact, as explained in Sec.IV, the gains from studies on stress related variations can be higher in the case of flexible electronics as the stress-induced variations in device performances could be exploited to predict more than the just the response of devices under various bending conditions.For example, the responses of devices spread on flexible substrates carry a signature of the shape of the substrate, and mapping these variations during bending could be exploited to obtain more information about UTCs than just getting the electrical responses.A combined outcome of these wide range of studies on stress/strain or piezoresistive effects has been a number of methods that are either used to minimize or compensate (e.g., when stress/strain is considered detrimental) the thermomechanical stresses during the chip fabrication assembly and packaging operations [33][34][35] or methods to improve performance or obtain more information about electronic substrate (e.g., when stress/strain adds value).
The modeling of piezoresistive and bending induced effects in flexible electronics is relatively a new development, 36 as can be noted from Fig. 2. A few papers have reported limited analysis related to the effects of externally applied stresses on device modeling and simulation. 37These include studies based on limited types of bending such as uniaxial stress-induced effects and using them to propose compact models and SPICE simulations. 38,39However, many other stress effects such as those related to external applied biaxial and shear stress are yet to be investigated.An in-depth analysis of such effects and their modeling, as presented in this review article, will consolidate the field and potentially boost the research on this topic, which, at the current rate, is expected to yield about 100 publications by the year 2020 (Fig. 2).A general theory about the effects of bending will also enable new CAD tools which are needed to analyze bendable ICs prior to the manufacture and to develop mitigation strategies.The optimum IC design for flexible electronics requires complete understanding and accurate compact modeling of external-induced stress effects in complementary metaloxide-semiconductor (CMOS) devices. 23

III. ULTRA-THIN CHIPS AND MECHANICAL BENDING
To understand the limits of reliable operation of UTCs, it is important to examine their mechanical properties in terms of bending strength, bending direction, thickness, and defect formation and failure.UTCs with thicknesses <20 lm have been explored by many groups to obtain a compact high-performance flexible electronics by using techniques such as post-process wafer thinning by grinding or chemical etching 30,40 (e.g., Circonflex process 41 ) and porous Si (e.g., Chipfilm TM technology 42 ).The strength of UTCs varies with the methods adopted to obtain them. 30,43For example, the 15-20 lm thick plasma treated UTCs have the highest strength of 2.34 GPa and can bend to R min ¼ 2.5 mm.On the other hand, the UTCs obtained by grinding and polishing can be deformed up to R min ¼ 33 mm.The UTCs obtained with the Dicing-by-Thinning process show the mechanical strengths ranging between 1.5 and 1.9 GPa for 70 lm thick samples (and between 1.6 and 2.7 GPa for 48 lm thick die). 44The flexible electronic systems are fabricated either (i) directly on flexible substrates (e.g., glass, steel, polyimide) [45][46][47][48][49] by processing methods such as batch 50 and rollto-roll 46,[51][52][53][54][55][56][57] or (ii) first on rigid substrates using the existing planar Si fabrication process and then transferred onto mechanically compliant substrates such as flexible plastic/ polyimide foils. 30,42As mechanical properties of various materials are different, the role they play in the variation of device performance during bending could vary and this needs to be considered as well.
The mechanical strength of UTCs could also vary with the packaging type or with the degree of electronics present on them.9][60][61] The 3-point bending [3PB, shown in Fig. 4(a)] tests (initially developed to test thick samples for fracture strength [62][63][64][65] ) on 8 lm thick UTCs reveal a mechanical strength of $3 GPa. 66Similar tests on UTCs embedded in flexible foil substrates 67 show an increase in fracture strength of up to $190% and a higher curvature of bending-which is up to $85% more than the UTCs which are not embedded in flexible substrates. 67Similarly, the mechanical strength of UTCs varies with the degree of electronics present on them.For example, 4-point bending [4PB, shown in Fig. 4(b)] tests have revealed that the blank (i.e., without active electronics) UTCs are mechanically stronger than those with CMOS circuitry. 43,53,55,56TCs can experience different types of deformations such as tension (the body is subjected to pull), compressive (the body is under compression), shearing (when the external load tends to make a part of the body to slide on the other one), and torsional (when the external load tends to twist the body around an axis). 68These deformation can be quantified in terms of stresses and strains having components such as uniaxial, biaxial, and torsional, as shown in Fig. 3. 68 Their analysis in UTCs is essential to: (a) understand the strength (the capacity to withstand strain and stress without breaking), stiffness (how much the system deforms and how is the load transferred within it), failure (mechanisms, causes, and modes), and stability (reliability of the equilibrium) limits, (b) design of multilayered structures such as 3D ICs, and (c) accurately characterize the CMOS devices.Assuming plane stresses, for a (x 1 , x 2 ) plane the stress tensor can be expressed as (engineering notation) as where r ij (i ¼ j) are the normal stress components and s ij (i 6 ¼ j) denote the shear stress components.These components depend on the coordinate system and vary from point to point inside the material.

A. Uniaxial bending of UTCs
Uniaxial deformation occurs when the applied bending moment(s) deforms the UTC sample along an in-plane axis [e.g., x 1 , as shown in Fig. 3(a)].In the 3PB test, an external load (uniformly distributed force F) is applied transversely along the middle line of the chip [Fig.4(a)], where the induced uniaxial stress is maximum. 93,94For small deflections, the maximum uniaxial stress, calculated using beam and plate bending theories, can be expressed as 68,95,96 where F is the applied uniform distributed force, b is the distance between the two internal points (Fig. 4), and h and B are the thickness and width of the plate, respectively.The thinner the chips are the more they deform.The finite element method (FEM) simulations indicate that the loaddeflection relationship is non-linear at large deformations. 44,97,98Not much has been reported in the literature about the analytical models that capture the nonlinear relationship between loading force and maximum stress.The 4PB test is another alternative to characterize the UTCs, which is preferred sometimes because of better load distribution between the supports to prevent the UTCs from failing prematurely. 99In this case, each point of the cross-section suffers both a rotation around the x 2 -axis and a displacement along the x 3 -axis. 100A uniform uniaxial stress r 11 is induced within the region between the two supports-tensile and maximum at the top of the sample, compressive and maximum at the bottom surface, and zero at the position of the neutral surface (red dashed line).In the case of UTCs, the curvature becomes very large and non-linear effects also appear.As a result, r 11 is calculated as 101 where R is the radius of curvature, E shows the Young's Modulus, and w is the beam displacement.The parameters are measured experimentally 43 or determined theoretically from FEM simulations 102 and x 3 is the coordinate along the out-of-plane direction.
In the case of UTCs packaged or embedded in thin foils, 103 several other factors, including increased thickness and the bonding/embedding, influence the bendability as compared to the blank or stand-alone dies.The controlled bending of such chips during characterization is achieved by FIG. 3. Distortion of the central-surface of an ultra-thin chip because (a) uniaxial bending along x 2 , (b) biaxial bending with respect to the x 1 and x 2 , and (c) torsion with respect to x 1 .50 0.2 a-Si:H (15% H) 78 130 0.2 a-Si:H (20% H) 78 110 0.2 nc-Si:H (SiH 4 4sccm/10sccm) 25-45/55-70 … Poly-Si 76,79 158 6 10 0.22 6 0.01 Epoxy Epotek 301-2 80 3.66 6 0.04 0.358 Polyimide Kapton 81 5.37 0.320 PEN 221 5-6 0. conforming them to a cylinder and then applying a uniform load, as shown in Fig. 5(a).The induced uniaxial stress in such samples, obtained by applying the load (stretching force q and bending moment M) to all layers, as shown in Figs.
5(b) and 5(c), is given by where e defines the position of the neutral plane.For an mlayer composite structure, e can be determined as 104 e ¼ For a single layer, Eq. ( 4) reduces to Eq. ( 2), and the neutral surface coincides with the middle surface.The analytical expression of strain can be obtained from Eqs. ( 4) and (5), by considering the Hooke's law. 45,46,68,1057][108] It can be noticed that Eq. ( 4) considers only the effect of M, and the effect of q is ignored.The uniaxial stress at the top of an assembly comprising a 20 lm UTC on 50 lm Kapton foil and conforming to a cylinder of R ¼ 10 mm in these samples has been reported to be jr 11 j h110i ffi 212 MPa and jr 11 j h100i ffi 173 MPa.The values of E are summarized in Table I.The bending investigations on UTCs (h ¼ 20 lm) with CMOS circuitry encapsulated in a polyimide foil show that 347 MPa uniaxial stress is induced in the chip, for a minimum bending radius R ¼ 5 mm. 109Likewise, a three-layer system (composed of 20 lm UTC, 10 lm epoxy glue, and 50 lm Kapton foil) bent on a cylinder of R ¼ 10 mm experiences uniaxial stress between [200 and 260] MPa, at the top of the chip, for applied M and variable jqj [0, 1] MPa mm. 88The breaking tests performed on UTCs with CMOS circuitry adhesively attached to thin substrates reveal $60% samples breaking at R ¼ 6 mm. 110

B. Biaxial bending of UTCs
UTCs also experience spherical deformations when bending moments are applied to both in-plane axes x 1 and x 2 [Fig.3(b)] or by a hydrostatic pressure applied on the entire surface.Biaxial flexural tests on plates, which have been used to evaluate the strength of ceramics for more than 40 years in various configurations such as ball-on-ring, 111,112 uniform pressure, 113 ring-on-ring, 114 or piston-on-threeballs, 115 have been adapted to investigate the biaxial strain effects in UTCs. 116,117,150Properties such as phonon or electronic deformation potentials 118,119 are measured through these tests to find the fracture strength 96,[120][121][122] or to investigate the 2D strain effects on the electrical behavior of MOSFETs. 123,124In the case of thin samples, the fracture strength is influenced by the roughness and morphology of the surface, 125 which in turn are affected by the surface defects introduced through backside grinding, polishing, chemical etching, and edge defects caused by wafer sawing or dicing.In terms of mechanical analysis, the spherical deformation of plates and shells is more complex than the cylindrical or uniaxial deformations.For small deflections, these stresses are expressed analytically, 68,69 and for large deflections (larger than the thickness of the Si-plate), they are usually determined by non-linear FEM calculations. 120ome examples are presented below.When a hydrostatic pressure p is applied to a thin Siwafer (e.g., thickness h ffi 280 lm) [Fig.6(a)], the induced stress can be expressed as a function of the pressure and radius of curvature R as 69,119,126 The pressure results in spherical deformation of UTCs.The experimental and 3D FEM simulations for UTCs with thicknesses of 15, 25, and 50 lm and an area of (10 Â 10) mm 2 indicate that the induced biaxial stresses are evenly present in the central area of the chip and they increase towards the edge. 117These studies also indicate that even if the singlecrystal Si is anisotropic, its biaxial elastic modulus ) is invariant for the (001)-Si crystal plane. 128Spherical deformation using pressure used in the case of islands of a:Si (100 nm grown on top of 400 nm Si 3 N 4 ) circuits fabricated on 50 lm thin Kapton foil 129,130 shows 5% average biaxial strain for every steradian spherical deformation (subtending 66 ).
The ball-on-ring test has also been used to investigate the fracture strength of spherically deformed UTCs. 67In the ball-on-ring method, cylindrical deformation is achieved with a force F, applied in the center of the sample with a conical steel punch head of diameter a, as shown in Fig. 6(b). 96,131The biaxial stress is observed at the central area of the wafer within a concentric circle of diameter d, where the induced radial stress equals the azimuthal (tangential) stress.With this bending method, an applied displacement of $0.9 mm induces $0.037% uniform biaxial strain in the center region of 100 mm wafers. 124The stress variation obtained by FEM simulations 124 and the maximum stress is calculated as 96,131 jr max biax j ¼ where d in turn can be expressed as a function of the thickness h and diameter a. 96,118,131,132 C. Torsional deformation of ultra-thin Si-chips The shear stress analysis in UTCs is also important for investigating their torsional fracture strength.A very few publications have reported the investigation of flexible layered Si-structures subjected to torque. 133Most of these investigations have been carried out by twisting bulk Sistrips around one axis (e.g., h110i or h100i) with test setup called torsional bridge. 134The torsional stiffness of bulk Si has been investigated since 1996 (Refs.135 and 136) and torsional tests have been used to determine the shear-moduli 137 and failure criteria. 138The maximum shear stress induced by a torsional moment at the surface of UTC depends on the applied moment, thickness, and the shear coefficients of the material UTC is made of.The rotational angle can also be calculated as a function of applied moment. 134Both the analytical results and the FEM simulation have been shown to have homogeneous shear stress induced at the surface with edges, thus offering an exception where the shear stress decreases rapidly.The shear stress analysis in UTCs can be described by the beam's theory based on small deformation assumption. 68The mechanical analysis of UTCs subjected to torque can be explained with Karman's plate theory 69 of large deflections.Since the deformation of such thin systems is accompanied by large rotational angles, the stress analysis often requires 3D FEM simulations.One of the few publications that deal with the torsional deformation of thin multilayer polymer systems used as substrates in flexible electronics is the study by Lee and Liu. 133Their results indicate that a sample having larger Young's modulus is easier to twist along the twisting direction than along the transverse direction and that the rectangular samples are easier to deform than the square ones.

IV. ELECTRICAL BEHAVIOR OF STRESSED SILICON AND CMOS TRANSISTORS
The effects of uniaxial, biaxial, and shear stress on the electrical behavior of strained Si-resistors and MOSFETs are further summarized in this section.The physical mechanisms by which various types of stress change the electron transport in Si are also highlighted.

A. Stress effects in bulk Si
Stresses change the electrical resistance of Si by significantly changing its resistivity even for small variation in geometry, 139 which is also termed as piezoresistivity. 140As Si is anisotropic, the variation in its conducting properties 141,142 as a result of stress can be expressed as

031101-6
Heidari, Wacker, and Dahiya Appl.Phys.Rev. 4, 031101 (2017) where r and q are the resistance and resistivity without stress, r kl and r mn are the components of stress tensor [Eq.( 1)], and P ijkl and P ijklmn are the first-and second-order piezoresistive coefficients.The cubic symmetry of Si results in a simplified piezoresistive tensor, 143 which can be evaluated for different Si-surface orientations and for uniaxial and biaxial stress.For the (001) Si-surface (which is prevalent in the microelectronics industry) and in-plane uniaxial stress, the 1st order piezoresistive tensor reduces to three independent piezoresistive coefficients (P 001 144,145 and the 2nd order piezoresistive tensor reduces to nine. 146,147or low stresses ( 500 MPa), the higher-order terms are usually neglected.
are the longitudinal and transverse piezoresistive coefficients.The angle h indicates the current flow direction and the angle u the stress application direction, as sketched in Fig. 6.These coefficients are determined from measurements along h100i-Si fundamental axes, which is also the principal stress axes (no shear stresses act along these directions).P 001 ð Þ 44 is the shear coefficient determined from h110i measurements as the uniaxial stress along these axes consists of both hydrostatic and shear components.The axes [ 110] and [110] are parallel and perpendicular to the primary wafer flat and correspond to the orientation of most resistors and transistors in ICs.A general relationship for the (001) Si-plane P (001) (P 001 Typical values of piezoresistive coefficients, obtained experimentally for uniaxial stresses up to 174 MPa, are given in Tables II and III. 144,147The piezoresistance coefficients depend on the impurity type and concentration.In conventional layout (Manhattan style), most transistors are built for h ¼ 45 .In that case, Eq. ( 9) becomes Á sin u Á cos u: where 12 .The piezoresistance coefficients for other Si-planes and crystallographic directions can be calculated by applying tensor rotation from the reference to the target Cartesian coordinate systems. 132,141For the (111)-Si plane, which is another common type of wafer used in IC fabrication, the uniaxial piezoresistive coefficients, for lightly doped n-type Si, with respect to the ( [ 110], [112], [111]) axes are B (B 1 , B 2 , B 3 ) ¼ (À312, 297, 61) (Â10 À12 Pa À1 ). 27The corresponding values for p-type Si are (718, 228, À448) (Â10 À12 Pa À1 ).In an n-type material, B 1 and B 2 are the largest coefficients whereas B 3 is quite small.On the other hand, in the case of a p-type material B 1 and B 3 have the largest values.
In the biaxial case, the stress is in-plane and symmetric r 11 ¼ r 22 and r 33 ¼ 0. The biaxial piezoresistive coefficient of Si is P B ¼ P L þ P T . 123The resistors and MOSFETs have been extensively studied to determine the variation of mobility of electrons and holes with biaxial stress and to analyze the electronic band structure of biaxially strained-Si. 148,149hese studies show that the electron mobility increases with tensile biaxial strain and decreases with compressive strain.The hole mobility increases with both tensile and compressive biaxial strain and is more pronounced in the case of compressive strain. 123,148These observations do not depend on the channel direction.The value of the shear piezocoefficient (P 66 ) in biaxially strained (001) p-type Si has been shown to increase for compressive biaxial strain and decrease in the case of a tensile strain. 149These observations are not always independent of dopant densities.For example, in the case of biaxial tensile strain, the decrease in the shear piezoresistive coefficient is more pronounced for low dopant densities, while for densities around 10 20 cm À3 , it remains unaffected.Further, the value of shear piezoresistive coefficients varies linearly with the compressive biaxial strain but is highly nonlinear in the case of tensile strain. 17The value of the shear piezoresistive coefficients also varies with temperature 150 -decreasing linearly and monotonically with the increase in temperature from À150 C to þ125 C. The  coefficient value can also change sign for low temperature and low doping as the strain is increased.This means that it may be possible to adjust the temperature dependence for strained-Si with specific doping and biaxial strain.The biaxial elastic modulus of Si often used in such investigations is B 001 ffi 181 GPa. 151he effects of strain are also reflected through change in the positions of atoms, bond lengths, and the angles between the bonds. 143For example, the high cubic symmetry (O h group) of the Si crystal is lowered with strain, which changes the energy band structure. 152The effect of changes in the energy band structure on electronics is reflected through variation in the effective mass and hence the mobility, as explained below.The band structure of crystalline Si in the first Brillouin zone consists of six ellipsoidal degenerate energy valleys [Fig.7(a)], which are also reflected through the cubic symmetry of Si.The ellipsoidal shape of the valleys can be characterized by two effective masses: 153 transverse m t ¼ 0.19m 0 and longitudinal m l ¼ 0.91m 0 , where m 0 ¼ 9.11 Â 10 À31 kg (511 keV) is the free electron rest mass.The electron conductivity effective mass of Si is proportional to the inverse of the sum over the effective masses in the different minima along the equivalent directions and is expressed as The applied strain lifts the original symmetry determined by band degeneracies and this leads to band warping 154 and changes the transport properties.The carrier mobility (l ¼ q m Ã Á s) also changes with resulting variations in the effective mass (m*) and the scattering rate (1/s) of phonons and impurities. 143In the case of n-type Si, the stress-induced band splitting causes the electrons to locate in the lowenergy valleys.As an example, the biaxial stress splits the conduction-band minimum, as shown in Figs.7(a)-7(c).This consists of six equivalent D 6 valleys in the unstrained state, four in-plane D 4 valleys and two out-of-plane D 2 valleys. 148On the other hand, in p-type Si the heavy-hole (HH) and light-hole (LH) valence bands minima are degenerated at the C point in the absence of stress as shown in Fig. 7(d).The tensile or compressive biaxial strain warps them significantly, with valence bands becoming highly anisotropic as shown in Fig. 7(e). 123,155,156Such effects change the conductivity and resistivity (q) of Si, which is related to the concentration of electrons (n) and holes (p) and their mobility l n and l p as q ¼ 1/(qn.ln þ qp.l p ), where q is the elementary charge. 157

B. Stress effects in MOSFETs
Various experiments on MOSFETs presented in the literature indicate that the mobility of charge carriers can vary with various stresses (tensile and compressive), as also explained previously in Section III.These variations can be directional as well as carrier type dependent.Generally, the channel direction differs from the stress direction.In a conventional layout, the MOSFETs are realized on the standard (001)-Si surface with current J flowing along h110i (Fig. 8).However, devices oriented along the principal Si highsymmetry axes h100i or processed on other Si-surfaces such as (110) and (111) are also often encountered.Therefore, the piezoresistive coefficient tensor should be evaluated separately from the channel mobility variation with stress.
Unlike bulk-Si, two aspects are specific to shear piezoresistive coefficients of the MOSFETs: First, in addition to the scattering on phonons and impurities, the carriers also experience Coulomb scattering at the oxide-Si interface. 158As a result, their surface mobility at room temperature is much lower than bulk Si (e.g., l n 670 cm 2 /V s versus 1400 cm 2 / V s for the bulk and l p 250 cm 2 /V s versus 450 cm 2 /V s for the bulk). 159,160The scattering takes place on the charges trapped at the interface and on the interface roughness. 143econd, the applied vertical electric field creates a potential well which confines the carriers in the out-of-plane direction, quantizing the energy levels and changing the effective mass in the out-of-plane direction.The degeneracy between inplane and out-of-plane valleys is removed.In n-type MOSFETs, the conduction band valleys shift and split the minimum into sub-bands D 2 and D 4 . 161Thus, even in the absence of strain, the energy levels are non-degenerate.The energy difference between the D 2 and D 4 sub-bands varies with the intensity of the transverse effective field.For example, an effective gate field of 1 MV/cm induces an energy difference DE 0 ¼ $12 meV, at T ¼ 300 K, for an inversion electron density of 10 13 cm 2 . 143The confinement field in the p-type MOSFETs shifts the degeneracy of valence band HH and LH sub-bands.A higher split can lead to lower interband scattering.In the case of (001)/h110i, the 1 MV/cm surface field causes a splitting of $25 meV, at T ¼ 300 K. 162 For (110)/h110i, the same field splits more the HH and LH subbands and causes a lower inter-band scattering, thus resulting in a higher hole's mobility than (001)/h110i Si.
In the presence of stresses, the band splitting due to the cumulative effect of both confinement-induced and straininduced band splitting.The strain alters the electrical characteristics of MOSFETs by changing the drain current I D through the effective carriers mobility l eff . 163This is the spatial average of the mobility profile in the inversion layer, which can be modeled by the universal mobility curve. 161The sensitivity of I D to stress is reported to have been caused primarily by the strain-induced changes of mobility. 164,165If the stress-induced threshold voltage variation is low, the I D variation because of stresses is governed by variations in l eff .Like Eq. ( 8), the change in drain current can be expressed as For the low stress values (<500 MPa), the piezoresistive coefficients are determined by variations of I D with stress in the linear or saturation regions of transistor characteristics.The piezoresistive coefficients can be calculated from the slope of mobility variation with respect to stress.These are significantly smaller in UTCs than their bulk counterparts, with values depending on the actual doping density and applied gate voltage.The piezoresistive coefficients also have some dependence on the channel length of MOSFETs.
The source-drain parasitic resistances to the drain current also contribute to such variations. 166For high stresses, the linear response piezo-model fails and the 2nd order terms must be considered.For (001) surface orientation and uniaxial stress, the piezoresistive coefficients are determined from uniaxial stress measurements in three cases: (a) longitudinal (stress k drain current I D k h110i); (b) transverse (stress ?(I D kh110i)); and (c) diagonal (/(I D , [110]) ¼ h ¼ 45 ) while stress is applied longitudinal and transversal to the channel. 167,168or n-type MOSFETs, the experimental results show that $100 MPa uniaxial tensile stress applied along h110i leads to $5% increase in the electrons l eff in the longitudinal case and only $2% in the transverse case. 39A few values of the piezoresistive coefficients are given below in Table III.For p-type MOSFETs, the hole mobility depends on the Si surface and channel orientation.The (001)/h110i MOSFETs show an inferior surface hole mobility than the (110)/h110i MOSFETs. 155This is due to a higher surface roughness scattering rate in (001)/h110i p-type MOSFETs than in (110)/ h110i p-type MOSFETs.The confinement field shifts the degeneracy of the HH and LH sub-bands.For example, a field of 1 MV/cm in a (001)/h110i p-type MOSFET, at T ¼ 300 K, induces a splitting between the HH and LH subbands as large as $25 meV. 162A tensile uniaxial stress of $100 MPa applied along the [110] direction causes an increase of $4.5% of the hole's mobility l eff in the transverse case and a decrease of $ À6% in the longitudinal case. 39,166The absolute values of the piezoresistive coefficients P 001 ð Þ 11 and P 001 ð Þ 12 of bulk MOSFETs are lower than bulk Si (Table III).However, the values of P 001 ð Þ 44 are similar.The differences arise from the presence of the confinement field in MOSFETs.In the case of the (111) Si-plane, the maximum mobility variation is obtained for the longitudinal case and the mobility variation is minimized when in the transverse case.
The studies related to the impact of stress on threshold voltage (V TH ) of nanoscale strained-Si and SiGe MOSFETs reveal that V TH decreases with increasing strain in the Si thin film.The V TH roll-off affects the device characteristics and performance.The analyses of V TH shift for uniaxial and biaxial stressed Si NMOS transistors with the h110i channel direction on (001) wafers show a significantly larger linear shift of the V TH (four times larger) for biaxial stress compared to the uniaxial case.This large variation in the biaxial case results from the stress-induced change in the Si electron affinity and bandgap.
The piezoresistive behavior of MOSFETs with similar configurations, under the same environmental conditions and in the presence of the same applied stress type and magnitude, is expected to be similar for devices on bulk Si and on UTCs.The difference between them arises from the mechanical stiffness (see Sec. III) related to the stress magnitude induced by a certain bending radius R. In this respect, UTCs in/on foils with different CMOS technologies have been reported to investigate the effects of piezoresistive behavior of MOSFETs.For example, short-channel singlecrystal-Si MOSFETs in a 0.8 lm CMOS process with 20 lm thickness on a 50 lm thick Kapton foil substrate have been studied by bending on cylinders of radii of curvature down to 10 mm. 88Smaller radii of curvature (R ¼ 5 mm) have also been reported with mono-crystalline NMOS and P-type Meal Oxide Semiconductor (PMOS) transistors 20 lm thick UTCs in a 0.35 lm CMOS process embedded into a polyimide foil, corresponding to a uniaxial stress r 22 ffi 347 MPa. 109Further enhancement in the minimum of radii of curvature (R [1.6, 70] mm) is achieved in a-Si:H thin-film transistors (TFTs) fabricated on 25 lm thick Kapton foil. 169

V. COMPACT MODELING OF STRESS EFFECTS IN CMOS DEVICES
As explained earlier, the stress leads to changes in semiconductor material properties such as change in band structure, effective mass, and electron affinity.From device viewpoint, all this is reflected in the changed mobility and threshold voltage, which eventually affect the device performance parameters such as drain current and transconductance.For an effective use of UTCs, an accurate and high-speed simulation of circuits based on a thin substrate is required.Currently, the simulation of the bending stress effects in ultra-thin devices is performed analytically using formulations available for understanding the analog operations.These effects are considered in conventional simulators for the planar architecture.Furthermore, due to the inherently slow simulation in the models based on numerical techniques, they are less desirable for ultra-thin devices.The performance indicators like accuracy, speed, and reliability are strongly connected to the compact models that are used to describe the device behavior, as also explained in Sec.I.This illustrates the importance of an accurate and efficient compact model for ultra-thin CMOS chips, which considers some of the stress/strain related variations discussed in Secs.III and IV.This section reviews the state-of-the-arts in this area.

A. Layout-dependent stress effects modelling
During the process of transistor isolation, it is a standard practice to make a shallow trench by etching the wafer and filling it with silicon oxide to isolate the active areas of MOSFET devices.This process exerts mechanical force, which is a compressive stress applied near to the diffusion areas.This stress is commonly referred to as the shallow trench isolation (STI) stress and termed as the Length of Oxide Diffusion (LOD) effect.Figure 9(a) shows the typical MOSFET layout surrounded by shallow trench isolation.SA and SB are the distances between trench isolation edges to Gate-polySi from the two ends.The LOD is expressed as  170 The charge carrier mobility of the device is influenced through the band structure modification, as explained in Sec.IV.Furthermore, the doping profile variation results in V th dependence of the stress effect.Both effects follow the same 1/LOD trend but have different L and W scaling influence.This underlined the importance of modifying some parameters in the BSIM model to implement the phenomenological model.
To model the mechanical stress effects impacting MOSFET electrical behavior, Bianchi et al. 171 presented a model which accounts for the mobility variations and experimentally evidenced with complex MOSFET geometries.This model proves to be an efficient way to include mechanical stress effects into standard simulation models.In this work, the STI induced mechanical stress has been shown to be the dominant mechanism for stress variation in the channel, which modulates the charge carrier mobility as a function of MOSFET geometry.
Another compact and scalable model about the STI induced mechanical stress effect on MOS electrical performance is given in Ref. 172.This model includes the influence of STI stress on the mobility, saturation velocity, threshold voltage, and other important second-order effects and therefore it could simulate the layout-dependence of MOS performance with greater accuracy and efficiency.The model has been verified with different technologies, different dimensions, and various layouts of MOS devices.Based on the model, new effective SA/SB formulas have been derived to improve the simulation efficiency and have also been verified by data from various layouts.An analytical model to estimate the delay in the presence of process-induced mechanical stress in stacked transistors based inverters and logic gates has been reported by Alam et al. 173 Derived using a modified alpha-power law, this model considers the channel length modulation effect.The methodology to incorporate the impact of processinduced mechanical stress effects in the derived delay model has also been presented.The incorporation of stress effects in this model enables estimating the layout-dependent effects of process-induced mechanical stress.The model has also been compared with Technology Computer Aided Design (TCAD) calibrated HSPICE simulation setup using 45-nm Predictive Technology Model.The model derives a stressaware delay model which is usable in the method of logical blocks like inverter and NAND/NOR gates.

B. Bending stress effect modelling
Several device modeling groups are dealing with the compact modelling of bulk MOSFET and advanced technologies such as double-gate (DG) MOSFET, 174 graphene FET transistors, 175 MoS 2 FET, 176 and CNTFET (Carbon NanoTube FET), 177 for analog and mixed circuits.The major goal is to bring simple solutions, which are numerically efficient and are close to device physics.These compact models also extensively explore the capabilities of Verilog-A and VHDL-AMS.However, only very few works have included the effect of stress in MOSFETs. 39,178n 2011, the authors reported a method to simulate the effect of uniaxial stress on MOSFETs. 39To calculate the coefficients for arbitrary directions of current and stress in the (001) silicon (Si) plane, the model implemented a general relation with the fundamental piezoresistive coefficients.This method can perform static and dynamic simulations in linear and saturation regions.It is simulator-independent and does not depend on the source of uniaxial stress.The model is adaptable to other bulk CMOS nodes as well as technologies such as Si-on-insulator (SOI).
The MOSFET device aging has also been studied and implemented with SPICE circuit simulation. 179For circuit simulation, the age-related degradation has been implemented as stress and associated key MOSFET parameters such as threshold voltage and mobility.The model operates with an optimization loop and starts the sequence with an initial set of parameters in Synopsys HSPICE as an external circuit simulator.It extracts device characteristic parameters including threshold voltage and drain current in the saturation and linear region.Subsequently, with an error function, the measured and simulated values have been compared to adjust the parameters and reach the minimum value of the error function.A compact model which demonstrates the simulations involving elastic deformation of a thin Si chip on a spherical holder is presented in Ref. 117.In this work, the simulation starts with a shell model which is validated through a convergence study and comparison with a 3D model.Following this, the influence of the anisotropic elastic behavior (single crystal) is considered in a bulge test condition and it was noted that isotropic and anisotropic Si simulation gave similar deformations.At the end, the spherical forming is accomplished with a shell model and an anisotropic law.
A deterministic compact model developed by Alagi et al. to investigate the parametric instability in elementary devices addresses the device instability, which can be traced back to microscopic reactions obeying the reversible firstorder kinetics. 180The model can describe the response to different periodic stimulus waveforms and is suitable for implementation in commercial electronic circuit simulators (Eldo UDRM).This methodology has been applied to model the negative-bias-temperature threshold voltage instability of a p-channel MOSFET.The comparator circuit simulated in this paper for threshold voltage recovery is crucial for circuit design.
A methodology to include parametric shifts induced by mechanical stress from wafer level chip scale package (WLCSP) in an analog circuit simulation flow is given in Ref. 181.Considering that the bending stress is homogeneous with packaging induced mechanical stress, their methodology enables analog system designers to identify circuit blocks with unacceptable sensitivity to WLCSP stress and provides a quantitative route for optimizing system floorplan and/or circuit layout.This is exemplified with an on-chip oscillator circuit suffering from an increased spread and yield loss caused by WLCSP stress variability.This issue has been resolved using a simulation flow which tuned using high-resolution experimental variability data measured on dedicated test chips.The method could be potentially useful for large area flexible electronics also.
Another interesting dimension of mechanical stress is its influence of the thermal behavior of devices.In this regard, the nonlinear model order reduction method is useful as it constructs the one-port dynamic compact models of nonlinear heat diffusion in UTC stacking technology. 182The method leads to models of small state-space dimensions and allows accurate reconstruction of the time evolution of temperature field due to an arbitrary power waveform of practical interest.This model has not been investigated for MOSFETs, but it helps us gather the information about the thermal behavior of UTCs.
Recently, Ojha et al. 183 presented a physics-based compact model for longitudinal and transverse stress profile in the channel of an uniaxially strained bulk MOS transistor.The model predicts the stress profile for linear stress (r L ), linear thickness (t L ), gate length (L G ), and gate height (h G ).The modeled stress profile is used to calculate the average stress and respective threshold voltage shift (DV th [V th (r L 6 ¼ 0) À V th (r L % 0)]) for different (h G ).The final strain induced V th model has only three fitting parameters and includes both the transverse stress component (S T , the stress component perpendicular to the direction of carrier flow) and the longitudinal stress component (S L , the stress component in the direction of carrier flow).Finally, the accuracy of the reported model has been verified by comparing it with the measured data obtained from devices fabricated using a 28 nm CMOS technology.Various bending induced effects described in Secs.III and IV can be used to develop a mathematical relation to describe the device model of the MOS transistor as where I D stress and V th stress are the new effective drain current and threshold voltage parameters including bending stress.I D 0 and V th 0 are the original drain-current and thresholdvoltage of the transistor without stress, respectively.The piezoresistive coefficients proportional to the drain-current and threshold voltage are reflected by P I D and P V th .r I D and r V th are the bending stress proportional to drain-current and threshold-voltage, respectively.The authors reported the implementation of Eqs. ( 15) and ( 16) using a language description in the Cadence environment to predict the value and orientation of the bending stress and describe the behavior of the transistor. 184Based on the three parameters (including drain-current, threshold-voltage, and orientation of the integrated transistor, which vary under the bending stress), a Verilog-A compact model was presented for MOSFETs developed in the standard CMOS technology.Figure 9(a) illustrates the CAD-based simulation flow by authors. 184It involves different abstract levels for both planar and bent MOSFETs.The labels A, B, C, etc., identify the blocks at various levels of simulation.From this model, one can note that there are significant performance advantages in process-induced uniaxial stressed n-MOSFET, exhibiting a smaller drain-current variation and threshold voltage shift by monitoring the bending stress and changing the supply voltage.The efficiency of this model was demonstrated recently with experimental results on 20 lm thick UTCs having devices and circuit realized in a standard CMOS technology. 185he measured and simulated transfer and output characteristic curves of NMOS and PMOS 0.35 lm transistors on a linear scale under planar, tensile, and compressive bending conditions are shown in Figs.10(b)-10(c).The maximum observed percentage difference in drain-current during bending for NMOS was found to be $5.9%, while the percentage difference of simulated results was 4.4%.For PMOS, it was found to be $2.4%, while the simulated difference was 2.17%.These results proved >95% accuracy of the proposed model to predict the effect of the bending stress on the devices.

VI. CIRCUIT-LEVEL STRESS EFFECTS
System is more than sum of its parts.In this regard, it is possible that the bending related effects observed in devices may or may not add up at the circuit level.Therefore, taking the discussion forward from devices to circuits, in this section we discuss the works where circuit level bending effects have been studied.We also use some of these circuits to establish the efficacy of Eqs. ( 15) and ( 16), which have been proposed to describe the stress induced changes in device response.These results open new avenues to predict the device behavior under various bending conditions and to explore the ways to compensate the bending effect or to take advantage of bending related changes extract more from the overall structure.For example, knowing the responses of devices spread over an area one can perform inverse calculations to predict the shape of substrates on which devices are present.This section also presents the methods that have been adopted to minimize or compensate the effects of bending in devices and circuits.7][188] Some of the circuits described in this section also use layout orientation to reduce the stress-induced effects.The mechanics and the electronic behaviors of various integrated circuits have been highlighted below (Tables IV and V).
A. Circuit-level bending stress effects

Inverters
CMOS inverters are one of the most widely used circuits.They operate at relatively high speed with very little power.During bending, the inverters on UTCs show deviation from expected response, because of the changes in responses of their constitutive FETs, i.e., PMOS and NMOS and the underlying physics.9][190][191] Only few of them have investigated the effect of bending stress on the performance.The performance of the thinned Si CMOS inverter circuit by Kino et al. 191 degrades under bending stress, as shown in Fig. 11(a) with MOSFET currents and CMOS inverter switching behaviors.It was observed [Fig.11(b)] that the switching threshold point, V sp , slightly increased after bending stress.The V sp increases with an increase in hole mobility or decrease in electron mobility as the b n /b p ratio increases under these conditions.Here, b p and b n are C ox W g /L g and C ox W g /L g , C ox , W g , and L g indicate the hole mobility, electron mobility, gate capacitance, gate width and gate length, respectively.The increase of V sp after bending shows that the compressive stress increases with V sp .Thus, local bending stress induced stress affects the CMOS inverter, leading to the circuit performance fluctuations in the Si chip.Another example by Sevilla et al. 189 reports thin (40 lm) and flexible (1.5 cm bending radius) Si based functional CMOS inverters whose characteristics show reduced performance for bending radii higher than 1.5 cm as shown in Figs.11(c) and 11(d).A comparison of these experimental results with the simulated output based on the compact model presented in Sec.IV B is shown in Figs.11(e) and 11(f).The good agreement of simulation results with the experimental characterization shows that the model presented in this paper through Eqs. ( 15) and ( 16) could be the starting point for analyzing device behavior under bending conditions.The effects of circuit-level stress on inverter performance investigated by Shahrjerdi and Bedell 205 show that the electron mobility increases with tensile strain and decreases with compressive strain.On the other hand, the hole mobility increases with both tensile and compressive strain but the effect is more significant for compressive strain because the hole effective mass decreases with compressive strain but increases with tensile strain. 161,205Since drain current is directly proportional to carrier mobility, higher drain current of the Si MOSFETs under strain can be attributed to high mobility. 192Therefore, the local bending stress affects the I-V characteristics of both MOSFETs in the inverter and so the switching behavior of the CMOS inverter.

Ring oscillators (RO)
The ring oscillator (RO) is cascaded combination of delay stages (inverters), connected in a closed loop.The ROs are of great interest to electronic engineers because of numerous useful application and features such as (i) oscillation at low voltage, (ii) high frequency oscillation, and (iii) low power dissipation and many more. 193Studying the effect of bending on 43-stage RO using a 250-nm process, Yuan et al. 194 noticed the speed enhancement under strained conditions.They have studied two types of inverter cell layouts: (i) PMOS channel is perpendicular to the NMOS channel and (ii) PMOS channel is parallel to the NMOS channel.A speed enhancement of $7.4% was noticed for uniaxial strain in a direction parallel to NMOS and perpendicular to PMOS.This is due to large current enhancement for both NMOS and PMOS.The speed enhancement for the second type of layout where strain is perpendicular to NMOS and parallel to PMOS was found to be only $1.5%, as no simultaneous enhancement for both NMOS and PMOS can be achieved.The mechanical study of ROs on the extremely thin flexible Si on insulator (ETSOI) process with a power supply voltage of 0.9 V also indicates a delay of $16 ps. 195The ultra-thin body of the Si channel in ETSOI devices allows aggressive scaling of the channel length into sub-20 nm range without incurring the detrimental short channel effects.Figures 12(c) and 12(d)  show the schematic illustration of RO used for a flexible Si solar cell and a flexible 20 lm thick Si, respectively.

Current mirrors
The current mirror is an important building block for linear integrated circuits especially amplifiers.In this circuit, the output current depends upon the aspect ratio, mobility, and feed current. 196There are clearly observable changes in the output current when the current mirror fabricated on thin Si experiences bending.This is because under the strained condition the mismatching between transistors gains prominence.
In an attempt to overcome the piezoresistive effects of bending to realize stable circuit, Hassan et al. 197 where l, r, and P are the mobility, stress, and corresponding piezoresistive coefficients, respectively.The circuits had a compact layout, fabricated using ChipFilm technology and were placed near the chip edges to reduce the chip warpage.

Operational amplifiers
Operational amplifiers (Op-Amps) are the commonly used components in circuit designs for amplification and sensor interfaces.Bendable Op-Amp design has become an increasingly interesting subject as many flexible sensors need them as an integrated part.9][200][201] Many of these have poor performance in comparison to conventional Si technology.For example, an a:Si op-amp 198 as a part of a 4-b digitalto-analog converter on a glass substrate, investigated for threshold instability in a time varying form, shows varying threshold voltage when Op-Amp is stressed.Another example is the non-Si Op-Amp based on IGZO TFTs 200 bent to a radius of 5 mm.The bent amplifiers show the same output behavior as the flat.The high-performance bendable op-amps on the polyimide substrate, realized with printed ribbons of single-crystalline Si, have a voltage gain of 4 dB, a unity-gain frequency of %100 kHz, and can be bent to a radius of 6 mm, which corresponds to a strain of 0.23%. 202nother example is the low noise amplifier (LNA) circuit realized by Kao and Chang 203 in a 0.18 lm technology on a thinned Si substrate of 90 lm.The LNA integrated with active and passive devices on plastic forms the front-end of a receiver.This work investigated the loss mechanisms of the parasitic effect of inductor before and after thinning of Si to 90 lm, but the effects of bending stress on the circuit performance were not provided.

Memory cells
The theoretical and physical limits of the traditional information storage technology have driven new generation data storage devices.To fabricate a fully functional flexible memory and prevent unwanted effects due to leakage current paths through adjacent cells, each memory cell must be integrated with a switching component such as a transistor.The high performance UTCs can meet flexible, fast, high-endurance, and scalable memory devices.A nonvolatile resistive random access memory (RRAM) array using a single crystal Si transistor and a memristor on flexible substrates was reported by Kim et al. 204 The n-channel MOSFETs transferred from a Si-on-insulator (SOI) wafer were used as a switching element of memory.A static random access memory (SRAM) cell is presented by Shahrjerdi and Bedell 205 as the integral element of system on chip (SoC) integrated circuits.In this work, bending tests were performed using circular cylinders with different radii of curvature (R) from 6.3 to 15.8 mm, shown in Fig. 13(a).The transfer characteristics of n-FET under different tensile bending conditions exhibit slight V th shift to smaller values (DV th ¼ 35 mV at R ¼ 6.3 mm).In these experiments, the bending was performed along the direction of the current flow in the (110) channel direction.Adequate stress management of UTCs is required to minimize the effect of bending stress.In this regard, additional enhancement to diminish warpage of UTCs has been investigated with Hybrid Systems-in-Foil (HySiF). 206The dummy structures for the upper metal interconnect layer have been used to reduce the stress originating from the final nitride/oxide passivation layer [Figs.13(b) and 13(c)].Additional enhancement with cancelling of bending stress effects on MOSFET is shown in Fig. 13(d). 207The achieved current at saturation for this particular device in UTCs (<5 lm) was 6.2 lA/lm with an on/off ratio of 3 decades, a threshold voltage of 0.36 V, and a subthreshold swing of 145 mV/dec.This indicates that the competitive metrics and the data for different bending radii can be improved through optimization and more advanced infrastructure.This type of minimization of process-induced stress for costefficient means of stress management could be an interesting future direction.Further improvements have been reported in UTC memory cells with a simultaneous roll transfer and interconnection of Si-based flexible NAND flash memory (f-NAND) based on a highly productive roll-to-plate anisotropic conductive film (ACF) packaging [Fig.13(e)]. 208In this study, an ultra-thin f-NAND chip is presented on an intermediate transfer substrate by bonding the Si NAND flash on a rigid glass and subsequently removing the handle wafer.They testified high performance specifications such as I on /I off ratio (>102 at V read ), reproducible endurance (>103 switching cycles), and long retention (>104 s).
In another report, electromechanical reliability of UTCs, including digital gates, was tested by the FleX TM Silicon-on-Polymer TM process where standard full thickness SOI wafers are transformed into flexible wafers and subsequently ultrathin physically flexible die. 209This work advanced the previous effort using single-crystal-Si MOSFETs in a 0.8 lm CMOS process with 20 lm thickness, bending on cylinders of radii of curvature down to 10 mm, 88 as shown in Fig. 13(f).
CMOS compatible metal-insulator-metal capacitors (MIMCAPs) on a mechanically flexible Si (100) fabric with 25 lm thickness have been reported by Rojas et al. as key components of dynamic random access memory (DRAM). 210he bending stress effects reported in this work indicate the mechanical robustness (minimum bending radius of 10 mm at an applied strain of 83.33% and a nominal strain of 0.125%) of devices and their consistent electrical behavior regardless of the applied mechanical stress.Recently, Kim et al. demonstrated a wearable and fully multiplexed Si nonvolatile memory array with nanocrystal floating gates. 211In this study, a deformable charge trap floating gate memory (CTFM) based on single-crystal Si has been fabricated under ambient conditions and process compatibility with conventional CMOS fabrication processes.The presented system measures the heart rates after exercise stress by interfacing with wearable Si amplifiers and on-board electrodes and stored in CTFMs.Accordingly, they used a pseudo-CMOS inverter composed of four n-type MOS transistors to amplify ECG signals and subsequently acquire the heart rate.

B. Circuit-level bending stress effect mitigation
The strategies to mitigate stress effects in flexible electronics or to exploit the new opportunity offered by bending is likely to gain more importance as the flexible electronics research makes way to the market.There have been few attempts to minimize or compensate the effects of bendinginduced stress on devices and circuits.The three main approaches which have been reported so far include (1) locating or embedding the device and circuits in the neutral plane, (2) distributed islands of rigid and stiff electronic components on flexible and stretchable substrates, and (3) optimal layout orientation for the circuits, possibly considering the expected bendability during use.A few examples of these methods are discussed below.
For reliable systems able to experience multiple bending during their lifetime, the UTCs are encapsulated between polymeric layers, particularly at the neutral surface in order to minimize the stress induced by deformation. 68,212,213The polymeric multilayer structures with simple circuit such as logic gates, inverters, ring oscillators, and differential amplifiers placed in the neutral surface have been reported by Kim et al. 188 to obtain flexible electronics with the minimal effect related to compression and tension.The 3-stage ring oscillator they fabricated using the printed single crystalline Si ribbon on the plastic substrate for studying the bending effect is shown in Figs.12(a) and 12(b).They reported slight but nonsystematic variations in the parallel channel ring oscillator on Si wafers under uniaxial strain.The speed enhancement is insignificant due to the simultaneous strain effect on both NMOS and PMOS.From this, it may be concluded that perpendicular channel ring oscillators prove to be more beneficial because of their high-speed enhancement under bending.
A differential amplifier integrated by combining nine transistors (a current source, a differential pair, and a current mirror) to provide a voltage gain of $1.4 for a 500 mV peak-topeak input signal shows that measured gains at various tensile strains vary by less than $20%. 188In this work, the stretchable differential amplifiers undergo tensile strain of 0% and 5%.A stable output is demonstrated with tensile strains up to 5%.Another example of using the neutral surface is reported by Hwang et al., 186 where the active layer is encapsulated by thin polymer layers, thereby placing the metal near the neutral mechanical plane.The distributed islands of rigid and stiff electronic components involve local modification of the flexible and stretchable substrates to mechanically support devices.Wagner's group at Princeton initiated this approach by integrating stiff islands of Si based devices and connecting them with compliant metallic conductors patterned on a soft substrate. 214,215The concept was broadened by tuning the local stiffness of a Polydimethylsiloxane (PDMS) substrate by controlling the cross-linking density. 216,2177][218][219] Recently, this approach has been improved toward a stretchable electronic substrate by employing multiple soft polymer layers patterned around silicon chips, which act as surrogates for conventional CMOS electronics chips, to create a controllable stiffness gradient. 220n terms of the optimal layout configuration to mitigate the stress and strain effects, Yuan et al. 194 reported a ring oscillator with different orientation layouts in each inverter cell.The two types of inverter cell layouts presented in this work include (1) the p-channel perpendicular to the nchannel (perpendicular layout) and (2) the p-channel parallel to the n-channel (parallel layout).The measurement results demonstrate a 7.4% speed enhancement of the ring oscillator with the perpendicular configuration under the uniaxial tensile strain to the parallel one.Accommodating the potential bending related changes at the design stage itself will be an interesting future direction.

VII. CONCLUSION
A review of recent progress on studies related to stressinduced effects in flexible electronics and their modeling have been presented in this paper.The focus of the paper was to analyze various stress/strain induced effects on the performance of electronics on flexible substrates and give new mathematical description of these bending induced effects to advance the CAD tools for designing of the next generation flexible electronics.The variations in the electrical parameters such as mobility, threshold voltage, and the device performance (static, dynamic) because of various bending induced stresses have been thoroughly presented.The effects of bending, material, mechanics, crystal axis, and band structure of the devices on UTCs have also been presented along with few strategies to compensate or minimize the effects of bending.The changes in the device and circuit response due to bending have been captured with mathematical relations, and their efficacy has been demonstrated by comparing the device output using these relations with experimental results reported in the literature.These results open new avenues for predicting the device behavior under various bending conditions and to explore the ways to compensate such effects.A few methods that have been adopted to minimize or compensate the effects of bending in devices and circuits have been discussed in Sec.IV.The minimization and mitigation of the bending effect by placing the device in the neural surface of the structure are popular and have been used in many of the circuits reported thus far for flexible electronics.The approach of using the neutral plane is attractive as it allows us to use the conventional planar fabrication and design tools, without worrying about the stress-induced effect, as the devices in neutral surfaces experience minimal or zero strain.However, this is not enough as it is challenging to fabricate all devices in neutral plane.Further for heterogeneous integration and 3D integration on flexible substrates, the neutral plane may not be possible and new methods will be needed to compensate the bending effects.The new knowledge will open avenues for further advances in flexible electronics.For example, with the knowledge of the response of devices spread over an area, one can perform inverse calculations and predict the shape of substrates on which these devices are present.This will be a new direction in the field of flexible electronics as the effects of bending, which were hitherto considered challenges to be overcome through various compensation methods, could be used to extract more information from bendable or conformable systems.Therefore, in addition to reviewing the current state of bending related effects in flexible electronics, this review paper also lays strong foundation for the new directions in flexible and large area electronics.

FIG. 4 .FIG. 5 .
FIG. 4. Classical flexural tests: (a) three-point bending (3PB) and (b) four point bending (4PB).F is the applied uniform distributed force.The neutral surface coincides with the middle plane of the plate and is shown in red.

FIG. 6 .
FIG. 6.Schematic representation of two classical biaxial bending tests used in the case of thin samples: (a) hydrostatic pressure; and (b) ball-on-ring.
are used instead of the fundamental piezoresistance coefficients.These are

FIG. 7 .
FIG. 7. Si conduction and valence bands as a function of biaxial strain.(a) The six Si conduction band valleys along three different directions are equally populated without strain; (b) schematics of bulk Si under biaxial tensile strain; (c) under tensile strain, the valleys are split into two groups.Electrons tend to populate the lower D 2 valleys than the higher D 4 valley; (d) and (e) show the three-top valence band near the C point for the strainfree and 1.5% biaxial tensile-strained Si, respectively.Reprinted with permission from Yu et al., Phys.Rev. B 78(24), 245204 (2008).Copyright 2008 American Physical Society.

FIG. 8 .
FIG.8.Common current flow (J) direction on (001) Si-plane.r is the uniaxial stress.The angle h indicates the current flow direction and the angle u the stress application direction, from the principal Si-axis.100

Figure 9 (
b) shows the stress distribution along the channel of MOSFET devices induced by the trench isolation.It can be noted that the stress of the central region increases dramatically with shrinking of the LOD.

FIG. 9 .
FIG. 9. (a) Illustration of MOSFET device geometry using a STI scheme.(b) Stress distribution within the MOSFET channel.Reproduced from Xi et al., Technical Report No. 94720 (University of California, Berkley, 2003).
investigated ultrathin (20 lm) CMOS current mirrors made up of orthogonally oriented transistors.The use of orthogonally configuration demonstrates the output current change (DI 2 /I 2 ) related to the transistor's changes of drain current (DI D /I D ) differences and can be written as

FIG. 11 .
FIG. 11.(a) Layout of Si microbumps and CMOS inverters in the thinned Si chip, and (b) CMOS inverter characteristic before and after bending.Reproduced with permission from Kino et al., Jpn.J. Appl.Phys., Part 1 52(4S), 04CB11 (2013).Copyright 2013 The Japan Society of Applied Physics.(c) Voltage transfer curve characteristics of flexible inverters at different bending downward radii and (d) upward radii.Reproduced with permission from J. Appl.Phys.Lett.108(9), 094102 (2016).Copyright 2016 AIP Publishing LLC.(e) Simulated results (based on the developed compact model) at different bending downward radii corresponding to the characterizations shown in (c).(f) Simulated results corresponding to the characterizations shown in (d) for different bending upward radii.

FIG. 12 .
FIG. 12. (a) Image of an array of ring oscillator; the inset on the right bottom shows the circuit diagram.(b) Dependence of the oscillation frequency on the supply voltage (VDD); the upper left inset shows output characteristics of an oscillator evaluated with a 10 V supply (VDD); the lower inset shows the variation in frequency as a function of bending radius and corresponding bending strain.Reprinted with permission from Kim et al., Science 320(5875), 507-511 (2008).Copyright 2008 AAAS.(c) Schematic illustration of a flexible Si solar cell.(d) Photographs of flexible 20 lm thick silicon.Reprinted with permission from Shahrjerdi et al., Solid-State Electron.117, 117-122 (2016).Copyright 2016 Elsevier.

TABLE OF CONTENTS
69

TABLE I .
Young's modulus and Poisson's ratio of some materials of interest.

TABLE VI .
Summarized comparison of flexible CMOS Inverters.V sp is the voltage of the switching threshold point. b