Enhancement-mode Ga2O3 wrap-gate fin field-effect transistors on native (100) β− Ga2O3 substrate with high breakdown voltage of channel temperature in Ga2O3 metal-oxide-semiconductor field-effect transistors by electrical measurements and thermal modeling

Sn-doped gallium oxide (Ga 2 O 3 ) wrap-gate ﬁn-array ﬁeld-effect transistors (ﬁnFETs) were formed by top-down BCl 3 plasma etching on a native semi-insulating Mg-doped (100) b -Ga 2 O 3 substrate. The ﬁn channels have a triangular cross-section and are approximately 300 nm wide and 200 nm tall. FinFETs, with 20 nm Al 2 O 3 gate dielectric and (cid:2) 2 l m wrap-gate, demonstrate normally-off operation with a threshold voltage between 0 and þ 1 V during high-voltage operation. The I ON / I OFF ratio is greater than 10 5 and is mainly limited by high on-resistance that can be signiﬁcantly improved. At V G ¼ 0, a ﬁnFET with 21 l m gate-drain spacing achieved a three-terminal breakdown

Gallium oxide (Ga 2 O 3 ) is emerging as a potential disruptive electronic material for high-voltage electronics applications. The excitement of this material is due to its (1) ultra-wide bandgap of $4.8 eV with $8 MV/cm theoretical critical field strength, 1 (2) up to four-inch native substrate availability and capability of melt-growth synthesis, 2 and (3) a wide range of n-type doping achievable by halide vapor phase epitaxy (HVPE), 3 molecular beam epitaxy (MBE), 4 low-pressure chemical vapor deposition (LPCVD), 5 metal-organic chemical vapor deposition (MOCVD), 6 and metal-organic vapor phase epitaxy (MOVPE). 7,8 The b-phase Ga 2 O 3 unit crystal has a monoclinic structure and is reported as the most thermally stable and conducive for the single-crystal homoepitaxial growth. 9,10 For heterogeneous integration, a notable cleavage plane is located along the (100) crystal plane, which has incited nanomembrane research for integration with arbitrary substrates and two-dimensional semiconductors. [11][12][13] The first transistor devices by homoepitaxial Ga 2 O 3 were demonstrated with a Sn-doped Ga 2 O 3 channel grown by MBE on (010) semi-insulating b-Ga 2 O 3 substrates. 1,14 Metal-oxidesemiconductor field-effect transistors (MOSFETs) followed later with a Si-doped channel and ohmic contacts by implantation with breakdown exceeding 750-V with a fieldplate. 15,16 Most recently, Sn-doped Ga 2 O 3 MOSFETs homoepitaxially grown by MOVPE on (100) semi-insulating b-Ga 2 O 3 achieved a record-high 3.8 MV/cm critical field strength surpassing GaN and SiC bulk theoretical field strengths. 17 For power electronics applications, a normally-off transistor is preferred for safe high-voltage operation and to mitigate off-state power dissipation. To achieve a highcurrent density, Ga 2 O 3 MOSFETs require high doping concentration resulting in a negative threshold voltage (V TH ). To shift toward positive V TH , non-planar fin-shaped channels offer enhanced electrostatic control of the channel by depleting it from the side walls without sacrificing doping. Achieving dense, parallel arrays of fin channels is most easily achieved by top-down plasma etching though reports of fin channels formed by metal-catalyzed wet-etching 18 and selfassembly 19 are promising to avoid plasma etch damage.
GaN-based fin-channel field-effect transistors (finFETs) have been reported with Si-doped GaN junctionless and high-electron mobility AlGaN/GaN heterostructure channels where the gate wraps around fins with enhanced electrostatics to nearly or fully deplete the channel. [20][21][22] However, the main drawbacks for GaN are cost and the availability of native substrates for low-defect density homoepitaxial growth. In this letter, we present a finFET with arrays of parallel Sn-doped Ga 2 O 3 fin channels formed by top-down plasma etching to achieve normally-off operation on a native (100) semi-insulating b-Ga 2 O 3 substrate. The results show the feasibility of wrap-gate architecture to shift the V TH to positive values while maintaining volume current densities for consideration in future high-voltage device design.
Fin-array field-effect transistors (finFET) devices were fabricated from a 300-nm Sn-doped Ga 2 O 3 channel grown homoepitaxially by MOVPE on a 100-mm 2 Mg-doped semiinsulating (100) b-Ga 2 O 3 substrate. 7,8,23 First, arrays of $300-nm wide fin channels with a $900-nm pitch were formed by electron beam lithography followed by 150-nm Cr metal evaporation as the hard mask. A second 200-nm Cr hard mask was superimposed on the fin mask by projection lithography to create bulk mesa contacts for source and drain electrodes. Both Cr layers were etched by inductively coupled plasma (ICP) etching using BCl 3 chemistry. 24 The etch conditions were 120 W reactive ion etching (RIE) power and 300 W coil power with 20 sccm BCl 3 and 16 mTorr chamber pressure. The etch selectivity of Ga 2 O 3 :Cr was approximately $2:1. To sufficiently remove the entire 300-nm channel between fins, an over-etch was required, which completely etched the fin Cr mask resulting in triangular-shaped fins. Residual Cr on the source and drain mesas was removed by commercially available Cr wet-etchant. Ohmic contacts consisted of Ti/Al/Ni/Au (20/100/50/50 nm) rapidly annealed for 1-min at 470 C in nitrogen. A 20-nm Al 2 O 3 gate dielectric was deposited by atomic layer deposition (ALD) at 250 C and patterned by fluorine-based RIE to allow for Ni/Au (20/ 480 nm) interconnects and $2 lm long optical gate metal evaporation. Finally, a second 20-nm ALD Al 2 O 3 layer was deposited and patterned on the sample to passivate the etched Ga 2 O 3 surfaces between interconnects. The fabrication process is illustrated in Fig. 1(a).
The finFET has a centered two-finger gate layout with each gate finger wrapping along 48 fins. The total source to drain distance (L SD ) is $4-lm, and the fin-array spans approximately $3-lm of this source-drain distance. A tilted SEM image of the fin channels with wrap-gate and bulk-like ohmic contacts is shown in Fig. 1(b). The sidewall morphology appears relatively smooth as previously observed using highpower ICP plasma etching with BCl 3 . 24 A representative cross-sectional SEM image of three fins is shown in Fig. 2(a). The darker contrast observed in the fin compared to the substrate is indicative of the Sn-doped channel and adequate electrical isolation between fins. Fig. 2(b) depicts that the fins are approximately $300 nm at the base with tapered sidewalls joining at $200 nm thickness. The 20-nm Al 2 O 3 gate dielectric and Ni/Au gate metal conform to the fin on all sides.
The mobility and doping concentration of the fins were measured from on-wafer Van der Pauw (VdP) test structures and device C-V measurements. It is widely reported that ionized donor concentration, N D , can vary significantly from the chemical Sn-doping concentration. 8,17 The sheet resistance (R SH ) and electron mobility (l) were measured on a VdP structure near the reported device as $40 kX/sq and $24 cm 2 / Vs, respectively. We observed the larger geometry of the Cr mask used for the VdP mesa etched slower compared to the Cr fin-array mask; therefore, the VdP mesa was protected during the fin-array definition process. A forward and reverse C-V measurement of the finFET is shown in Fig. 3 indicating $0.8 V of hysteresis, which has been previously reported as mobile border traps in accumulation. 25 In the inset, an N D $ 2.3 Â 10 17 cm À3 was extracted from the linear region of 1/C 2 as a function of V GS . The area was estimated as L G W fin N fin where W fin is $200 nm after considering a $70 nm backside depletion width and using a 3:2 width-to-height triangular fin cross-section. Finally, the flat-band capacitance, C FB , can be calculated by the measured oxide capacitance (C ox $ 225 fF) in series with the semiconductor capacitance (C S ). 26 The corresponding forward and reverse sweep flatband voltage, V FB , is 1.3 V and 2.1 V, respectively.
In the absence of accurate models for Ga 2 O 3 , onedimensional analytical expressions were used to estimate the depletion widths (W d ) on the two sides and bottom facet of the Sn-doped fins. The partial depletion width of the sides in the ungated region can be estimated by the built-in energy potential (V bi ) using the energy band lineup at the Al 2 O 3 / Ga 2 O 3 interface 20 (2) where V t and N C are the thermal voltage ($26 mV at 300 K) and effective conduction band density of states for Ga 2 O 3.

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This analysis shows E C ÀE F is $73 meV and leaves a nonnegligible V bi(ug) $ 1.4 eV, which may be related to interface traps and/or pinning, which is neither well-understood nor reported.
A similar study of GaN finFETs deduced a V bi $ 0.74 eV in the ungated region and was explained by Al 2 O 3 /GaN interfacial chemistry by XPS. 20,29 Furthermore, in the gated region, the band-bending can increase an additional $1.15 eV due to the difference in metal work functions of Ni (A m ¼ 5.15 eV) and Ga 2 O 3 20 where v s is the electron affinity of Ga 2 O 3 ($3.5 to 4.0 V). 27,30 However, this does not consider trap-assisted tunneling for thin Al 2 O 3 gate oxide, 27 and it remains unclear how the V bi(ug) compensates for the band-bending normally induced by a gate contact without thorough XPS characterization of our particular interface. For a simple case, however, where both energy barriers are combined in the gated region, the V bi(g) is $2.5 V, which is reasonably close to the measured reverse sweep V FB . The maximum depletion width, W d , for each region is calculated by the following equation: where e o and e S are the permittivity of free space and Ga 2 O 3 dielectric constant, respectively. This yields W d $ 83 nm and $110 nm in the ungated and gated regions, respectively. A backside depletion width from the semi-insulating substrate is found to be $70 nm assuming a mid-gap interface trap density of $2 Â 10 17 cm À3 . 17,31 Therefore, we estimate an undepleted fin with approximately $26 nm (base) Â $ 17 nm (height) in the ungated region contributes to the volume conduction mechanism in the finFET. In contrast, the depletion from the sides and substrate fully deplete the fin dimensions in the gated region to realize the normally-off operation. It should be noted that once V GS > V FB , the finFET is operating in accumulation similar to non-planar normally-off junctionless GaN finFETs. 20,32 Fig. 4(a) shows the family of I D -V D curves from V GS ¼ þ4 V to 0 V. At V GS ¼ þ4 V, the on-current (I ON ) reaches $3.5 lA. An upper bound on expected current in the partially depleted fin-arrays can be approximated by the open channel current density (J n ) where V DS < jV GS -V TH j using the drift current equation where E CH ¼ V DS /L CH is the potential across the source-drain channel (L CH ). Using the partially depleted fin-array crosssectional area at V DS ¼ 2 V and L CH ¼ 3 lm, J n ¼ 5.9 kA/cm 2 or I D % 1.3 lA, which is close to the measured value in Fig.  4(a). For comparison, this simple analysis is also in agreement at V DS ¼ 1 V (I DS ¼ 0.55 mA) for the planar Sn-doped Ga 2 O 3 MOSFET reported by Green et al. using the surface and substrate depletion widths with the reported N D and Ti/Au gate. 17 The gate width, W G ¼ W fin N fin , is $19 lm corresponding to an I ON $ 0.18 lA/lm. The low I ON is a main limitation of the fin-array topology reported here, but can be drastically improved in the future with higher-mobility materials and onresistance optimization. For this device, the gate swing was limited by the conduction band offset of Al 2 O 3 /Ga 2 O 3 , which can be improved with, for example, ALD SiO 2 . 33 The gate leakage characteristics are shown in Fig. 4(b) and indicate ultra-low gate leakage near 10 À12 Amps before an onset of trap-assisted tunneling at forward bias appears. 27 Fig. 4(c) shows the I D -V G characteristics at V DS ¼ 10 V. Despite I ON limitations, the finFET has >10 5 I ON /I OFF ratio. The device reaches an off-state approaching 10 À12 Amps between 0 and þ1 V GS indicating enhancement-mode operation. To rule out the parasitic conduction in the substrate  between fins, an identical MOSFET with the epitaxial channel etched away was fabricated and shows minimal modulation of the remaining etched SI substrate. We attribute this parasitic modulation to uncompensated free carriers in the substrate being accumulated at the Al 2 O 3 /SI-Ga 2 O 3 interface. The forward and reverse sweeps reveal trapping effects that may be a combination of the unoptimized Al 2 O 3 /Ga 2 O 3 interface and density of interface traps (D it ) caused by the plasma etching of the fin side walls. Despite no surface treatment optimization, the subthreshold slope (SS) is 158 mV/dec, which is superior to previously reported Ga 2 O 3 MOSFETs. The D it can be estimated by the shift in forward and reverse V FB from Fig. 3 using the following expression: which is approximately $3.9 Â 10 11 cm À2 eV À1 where C ox $ 3.8 fF/lm 2 . The area for C ox is calculated using the measured C ox , 20 nm thickness and a gate dielectric constant of 8.5; though, estimating the area using the sum of the fin side facets multiplied by L G gives nearly the same value. This D it value is similar to previously reported Al 2 O 3 /Ga 2 O 3 and SiO 2 /Ga 2 O 3 MOS capacitors on (-201) n þ b-Ga 2 O 3 substrates with D it < 1.0 Â 10 12 cm À2 eV À1 after surface treatment optimization. 33,34 The effect of surface plane orientation of the fin facets and the dielectric-Ga 2 O 3 interface quality is unclear and requires further investigation.
FinFET high-voltage operation on wider devices with L GD ¼ 16 lm and 21 lm was characterized with an Agilent B1505A on a Cascade Tesla probe station. At V GS ¼ 0 V, the I DS is <10 À7 Amps until a breakdown voltage (V BK ) is reached. For each L GD , a V TH ¼ þ0.8 is measured at V DS ¼ 10 V, which is shown by the inset of Fig. 5. It should be noted that the I ON for large L GD devices have a very high onresistance and do not saturate at V DS ¼ 10 V. At V GS ¼ 0 V, a V BK was measured at 567 and 612 V for L GD ¼ 16 and 21 lm, respectively. As indicated in Fig. 5, V BK is destructive and limited by peak electric fields in the gate oxide.
To conclude, we have fabricated an enhancement-mode Ga 2 O 3 MOSFET enabled by arrays of Sn-doped fins on a semi-insulating (100) b-Ga 2 O 3 substrate. A V BK exceeding 600-V at V GS ¼ 0 V off-state was demonstrated and represents the highest breakdown voltage measured without fieldplate for b-Ga 2 O 3 transistors, and the highest breakdown for any transistor technology utilizing non-planar device channels. [20][21][22][35][36][37] Future work includes understanding the role of traps at the dielectric-Ga 2 O 3 interface and optimizing onresistance by reducing the fin channel length and using highly doped ohmic cap layer.