Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (VTH) in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We attribute this to charge trapping/detrapping and charge migration within the gate dielectric. We emphasize the fundamental difference between trapping/detrapping events occurring at the semiconductor/dielectric interface and those occurring at gate/dielectric interface, and show that charge migration is essential to explain the first anomaly. We model charge migration in terms of the non-instantaneous polarization density. The second type of anomaly is negative VTH shift under high positive bias stress, with logarithmic evolution in time. This can be argued as electron-donating reactions involving H2O molecules or derived species, with a reaction rate exponentially accelerated by positive gate bias and exponentially decreased by the number of reactions already occurred.

Amorphous oxide semiconductors (AOS) such as amorphous indium-gallium-zinc-oxide (a-IGZO) are strong candidates for post-silicon electronics, especially for thin film transistor (TFT) applications. 1,2Since any unintentional change in TFT characteristics can affect systems reliability, the stability of TFTs is a topic requiring a constant research, especially when TFTs are fabricated at low temperature using new materials and new processes.It is commonly understood that IGZO TFTs fabricated at high temperature (> 300 o C) have achieved the level of stability sufficient for many of application. 35][6][7] However, on the way to achieving this state-of-the-art, we have come across devices with large threshold voltage (V TH ) shift or anomalous behaviors, and understanding the cause of this is of fundamental importance.In this context, we report in this paper the anomalies observed in AOS TFTs under bias stress in the dark, and discuss possible mechanisms.
Since current flow in a semiconductor is proportional to the number of free electrons, any V TH shift can be viewed as a change in the n free -V GS curve, where n free is the number of free electrons per unit area in the AOS channel and V GS the gate-source voltage.n free depends on the concentration of induced charge (n ind ), and the ratio between n free and n ind follows the Fermi-Dirac distribution.Hence it depends on the Fermi-level (E F ) and the density of states (DOS) profile.Two key mechanisms to explain V TH shift in TFTs under bias stress are charge trapping into the gate-dielectric and defect creation in the semiconductor layer.When charges are injected into the gate-dielectric, E F in the semiconductor layer is shifted.Hence so is the n free -V GS curve and V TH .When defects are created in the semiconductor layer, the DOS profile may change.This changes the dependence between E F and V GS , resulting in a non-parallel shift of the drain current (I D ) versus V GS curve.The first type of anomaly observed is illustrated in Fig. 1, where we can see that V TH shifts to the opposite direction of the applied bias, i.e., negative V TH shift under positive bias stress (PBS) and positive V TH shift under negative bias stress (NBS).The TFT has a co-sputtered Ta 2 O 5 -SiO 2 gate-dielectric, sputtered zinc-tin-oxide (ZTO) channel, SiO 2 etch-stopper layer, sputtered Mo source-drain, and sputtered MoCr gate, with a bottom-gate staggered structure as illustrated in Fig. 1(d).All TFTs used in this work have the size of W/L = 45 µm/45 µm, and fabrication steps were performed below 150 • C. For reference, bias-stress results of a TFT with the usual behavior (i.e., positive V TH shift under PBS and negative V TH shift under NBS) are shown for comparison.The TFTs were identical, except for the gate-dielectric material, which was silicon nitride (SiN x ) deposited by PECVD (plasma-enhanced chemical vapor deposition).When this anomaly is present, we observe counter-clockwise hysteresis in the I D -V GS curve because of the bias-stress induced during characterization, as depicted in Fig. 1(c).It is worth emphasizing that this behavior, as well as the second type of anomaly discussed later, was observed not just in a single TFT but in all devices in the same fabrication run.This type of anomaly was observed in our samples having Ta-or Zr-based oxides as the gate dielectric, and also reported by other groups for Hf-or Ta-based oxide FIG. 2. (a) Four possible trapping/detrapping events, at the interface between semiconductor and gate dielectric (to explain V TH shift in the usual direction) and at the interface between gate metal and gate dielectric (to explain the first anomaly).(b) Change of induced charge after electron trapping from semiconductor to gate dielectric or after electron detrapping from gate dielectric to gate metal, under assumption of no charge migration.][10] Since this anomaly is highly dependent on the gate dielectric material, we identify two possible mechanisms: charge trapping/detrapping and charge migration within gate dielectric.
The basic concept of the charge trapping/detrapping mechanism is that the change of the net charge in the gate dielectric changes the number of induced electrons, resulting in V TH shift.Figure 2(a) schematizes four possible trapping/detrapping events considering two different interfaces (between semiconductor and gate dielectric, or between gate metal and gate dielectric) and two different directions (into or from the interface).When electrons are trapped from the semiconductor into the gate dielectric under PBS, or trapped from the gate metal into the gate dielectric under NBS, the net charge of the gate dielectric becomes more negative.Thus the number of induced electrons in the channel becomes smaller, resulting in lower current, which yields a positive V TH shift.On the other hand, if electrons are detrapped from the gate dielectric to the gate under PBS or to the semiconductor under NBS, the net charge of the gate dielectric becomes more positive, inducing more electrons in the channel.This results in negative V TH shift.Here, we note that the usual V TH shift direction is caused by the trapping/detrapping events occurring at the interface between the semiconductor and the gate dielectric, and the first type of anomaly is caused by the events occurring at the interface between the gate metal and the gate dielectric.Although the argument based on trapping/detrapping seems to explain the observed anomaly, we would like to bring charge migration into consideration.In order to show the importance of this second mechanism, we do a simple analysis of a TFT under bias stress with the following assumption: trapping/detrapping events occur at the very interface, so that the spatial charge location does not change at all during trapping/detrapping events (i.e.no charge migration).We consider the TFT under PBS, with negative charge -Q in the semiconductor, positive charge +Q in the gate metal, and zero net charge in the gate dielectric, as schematized in Fig. 2(b).If electron trapping occurs at the interface between the semiconductor and gate dielectric, the net charge of gate dielectric becomes -Q trap , and the charge in the semiconductor becomes smaller: -(Q − Q trap ).However, on the basis of our earlier assumption that trapping/detrapping event does not involve spatial charge location change, the charge in the gate metal remains the same as before, regardless of what happened at the semiconductor/dielectric interface.Analogously, if electron detrapping happens at the interface between the gate metal and gate dielectric, the charge in the semiconductor does not change.This analysis shows the fundamental difference between the events occurring at two interfaces.When we assume no charge migration, trapping/detrapping at the interface between the semiconductor and the gate dielectric changes the charge in the semiconductor, resulting in a V TH shift.However, if the event occurs at the interface between the gate metal and dielectric, the charge in the semiconductor remains the same, and hence no V TH shift.
The analysis above shows that the trapping/detrapping mechanism alone cannot explain the first type of anomaly if we don't consider the charge migration.In the case of an ideal dielectric material between two parallel metallic plates, the electric field (E) and induced charge (Q) have the following relationship: where A is the area of the metallic plate, ε 0 the permittivity of free space and P the polarization density in the dielectric material, which can be written in terms of the electric susceptibility ( χ) or dielectric constant (ε r ): The time necessary for the dielectric material to become polarized can be considered instantaneous when we compare with the typical time range of electric characterization of TFTs.We now consider, for example, a proton moving from one position to another inside dielectric material, as illustrated in Fig. 3.This movement needs to overcome energy barriers, which makes it a non-instantaneous event.The position occupied by the proton before the migration now lacks positive charge, so the net charge at that position becomes more negative than before.By the same, FIG. 3. Charge migration within gate dielectric, which introduces non-instantaneous polarization density.

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Jin et al.AIP Advances 6, 085321 (2016) the current position of the proton is now more positive.So the charge migration can be viewed as creation of a dipole, which brings an additional polarization density in the dielectric material.Now, the induced charge can be written as: where subscripts i and ni mean instantaneous and non-instantaneous, respectively.Note that Q is a time-dependent quantity now.From the definition of polarization density, P ni (t) can be written as: where Vol denotes volume of the dielectric material, N the total number of such dipoles, q the dipole charge and d the dipole length.Under bias stress, N, d, and consequently P ni and Q increase over time.
In the case of a TFT under PBS, the negatively charged plate in Fig. 3 corresponds to the semiconductor layer.With the additional polarization density, we have, for a fixed V GS value, more electrons induced in the semiconductor, which means higher current and negative V TH shift.In the case of NBS, the positive side is the semiconductor.So the polarization density is in such direction that decreases the number of electrons in the semiconductor, meaning lower current and positive V TH shift.The charge migration argument successfully explains the first type of anomaly.
The second type of anomaly, which is negative V TH shift observed under high positive bias stress (HPBS), is depicted in Fig. 4. The TFTs with this anomaly were fabricated in the same fabrication run and had sputtered IGZO as the channel material, PECVD-deposited SiNx as the gate dielectric and PECVD-deposited SiO 2 as etch-stopper layer, with the same bottom-gate structure as Fig. 1(d).Figure 4 summarizes V TH shift of these TFTs after 5 minutes of stress and 5 days of recovery, with several stress biases (V ST ) from −30 V to +35 V, with drain and source commonly grounded, at ambient temperature.For each V ST condition, a different TFT was used.We note large negative V TH shift under NBS and small positive V TH shift under low positive bias stress (< 20 V), which are in the normal V TH shift direction, thus ruling out charge migration.The recovery of V TH shift under HPBS is very slow and incomplete (e.g., ∆V TH = −2.8V in 5 minutes of +30V stress; 0.3 V recovered in 5 days), which is much smaller compared with the first anomaly.
Although negative V TH shifts are observed under both NBS and HPBS, their mechanisms are independent.When we apply NBS to a TFT previously stressed under HPBS condition, the TFT shows a fast and large negative V TH shift, as shown in Fig. 5(a).If we apply NBS first and then HPBS, we observe a similar behavior, as seen in Fig. 5(b).We compare two cases, HPBS (1 minute of +30 V stress) applied to two differently stressed TFTs: HPB-stressed (5 minutes of +30 V; case 1), and NB-stressed TFT (5 minutes of −30 V; case 2).If the same mechanisms were responsible for both HPBS-and NBS-induced negative V TH shifts, we would expect a small V TH shift in both cases, which is not the observed result.Another interesting result is that the negative V TH shift under HPBS systematically shows a logarithmic time dependence.The V TH shifts under V ST from 26 V to 35 V are shown in Fig. 6 where we observe that each curve is well described with logarithmic fit: Extracted values of fitting parameters B and τ are plotted in Fig. 6(b), and the quantity B/τ is plotted as a function of V ST in Fig. 6(c).This quantity shows a good exponential fit.It is of particular interest when we translate the V TH shift in terms of number of induced electrons (n ind , per unit area): and we can write the change rate dn ind /dt as a function of n ind : where C i is the capacitance per unit area of the gate dielectric and q the elementary charge.As we have empirically observed that B/τ is an exponential function of V ST , we can write the change rate as the following: where K is constant and ψ ST is a function of V ST .This kind of kinetics is similar to that of oxidation of metallic surfaces by gas adsorption 11,12 or by electrosorption of OH species in ionic solutions, 13 implying that the increase of the number of electrons may be due to chemical reactions generating free electrons in IGZO layer, with ∆n ind representing the number of occurred reactions.Here, H 2 O is a strong candidate involved in the reaction.It is known that IGZO TFTs stored under high humidity condition shows negative V TH shift over time. 14,15It has also been reported that PBS test under high humidity condition results in negative V TH shift in IGZO TFTs. 16In Ref. 17, the authors propose that the SiO 2 etch-stopper layer embedded with H 2 O molecules may cause negative V TH shift under PBS, releasing extra electrons to IGZO.So we propose that equations ( 7) and ( 8) may be interpreted as electron-donating reaction rate involving H 2 O molecules or derived OH species that are present in the TFT from fabrication process or from interaction with ambient air during storage.We suspect that these species are located in the SiO 2 etch-stopper layer in accordance with Ref. 17, but we do not exclude the likelihood of the semiconductor or gate dielectric layer being contaminated.
In summary, two different types of anomalies in AOS TFTs have been observed under bias stress.The first is characterized as V TH shift in a direction opposite to the applied bias, and we have shown that charge migration within gate dielectric is the crucial mechanism.Charge trapping/detrapping alone cannot explain the anomaly due to the fundamental differences between the events occurring at the two different interfaces.The second is negative V TH shift under high positive bias stress, with logarithmic evolution over time.We argue that this is caused by electron-donating reactions, involving H 2 O molecules or derived OH species.
FIG. 1.First type of anomaly (red), with (a) negative V TH shift under PBS and (b) positive V TH shift under NBS.For comparison, V TH shift of a TFT with usual behavior is plotted (black).(c) Counter-clockwise hysteresis observed in TFTs showing the first type of anomaly.(d) Bottom-gate staggered TFT structure employed in experiments.

FIG. 4 .
FIG. 4. Second type of anomaly, with negative V TH shift under HPBS.Figure shows V TH shift of IGZO TFTs under 5 minutes of stress (V ST from −30 V to +35 V) and after recovery of 5 days.

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FIG. 6.(a) Evolution of V TH shift under high positive bias stress, with logarithmic fits.Extracted values of (b) coefficient B (black), τ (red), and (c) B/τ are plotted as a function of V ST , with error bars indicating the standard error of the regression.Quantities B and B/τ are compared with linear and exponential fit, respectively.