Fabrication and evaluation of series-triple quantum dots by thermal oxidation of silicon nanowire

Title Fabrication and evaluation of series-triple quantum dots by thermal oxidation of silicon nanowire Author(s) Uchida, Takafumi; Jo, Mingyu; Tsurumaki-Fukuchi, Atsushi; Arita, Masashi; Fujiwara, Akira; Takahashi, Yasuo Citation AIP advances, 5(11) Issue Date 2015-11 Doc URL http://hdl.handle.net/2115/60524 Rights(URL) http://creativecommons.org/licenses/by/3.0/ Type article File Information 1.4936563.pdf


I. INTRODUCTION
The fabrication of capacitively coupled quantum dot devices composed of more than two quantum dots have been attractive for quantum information processing. 1,2 Realizing quantum computations by extending the number of coupled quantum dots is the ultimate goal. Initially, a singlequantum-dot devices exploiting the two-dimensional electron gas (2DEG) formed within semiconductor heterostructures were studied for single-electron tunneling phenomena 3,4 and functional electronic devices, such as single-electron transistors (SETs). 5,6 Multiply-coupled quantum dot systems were first investigated in devices for single-electron transfer such as the single-electron pump and turnstile, and fabricated using metal dots. 7,8 To fabricate coupled multiple-quantum-dot devices more flexibly, gate-defined quantum dots were formed in the 2DEG by attaching fine gate electrodes on the surface. [9][10][11][12] The great advantage of this technique is that the configuration and formation of the quantum dots is tunable by adjusting tunnel barriers between the quantum dots by controlling the voltages applied to the gates surrounding the dots. Gate-defined coupled quantum dot devices have revealed details of electron transport of double, triple, and quadruple-quantum-dot coupled systems. [13][14][15] Although the devices are useful in confirming the principle of single-electron transport and quantum computing, complicated structures with many gate electrodes are needed to form the various coupled quantum dots, and in consequence the devices are not sufficiently integrated. Therefore, a new technique is required to fabricate multiply coupled quantum dots into a compact device that has a minimum number of gates attached.
With this in mind, silicon-based quantum dots have attracted interest because of higher operating temperatures and the operation stability. 16,17 In addition, by taking advantage of their long spin coherence times, their functioning as a spin-based qubit was demonstrated in a double-quantumdot device. [18][19][20][21][22][23][24] Recently, triple-quantum-dot devices have been demonstrated and analyzed for multiple qubit capability and other applications, such as for turnstile operations. [25][26][27][28] These studies are suggesting the many advantages of silicon-based technology in fabricating coupled nano-dots.
Pattern-dependent oxidation (PADOX) is well known as a very simple technique in single quantum dot fabrication [29][30][31][32] because it automatically converts the one-dimensional silicon nanowire to a single nano-dot along with the tunnel barriers on both sides of the nanowire by using band modulation originating from quantum-size effects and the effects of strain that have accumulated during thermal oxidation. 30 Because thermal oxidation reduces the size of a Si dot from that of the initial nanowire defined by the lithography, PADOX-formed quantum dots are expected to have a high operating temperature because of their smaller size. 33 However, the PADOX technique is suitable only for making a SET with a single dot because it is too sophisticated to form a dot in the middle of the nanowire. Despite the difficulty in controlling the configuration of the quantum dots, some multiple-quantum-dot fabrications have been demonstrated using PADOX to introduce lithographically a modulation in the nanowire width. 28,[34][35][36] Manoharan et al. fabricated using this technique an asymmetric triple-quantum-dot device that had a larger central dot and smaller side dots. 28 However, with this technique, it is crucial to modulate the wire width to form the multiple islands. Such patterning is complicated and lacks the flexibility in device design.
Double-quantum-dot devices have previously been fabricated by applying PADOX to a Si nanowire and additional oxidation of the nanowire in the gap between the two fine gates attached on the nanowire. The characteristics of the double quantum dots have been obtained. 37 However, details of the formation of these dots are still unknown as the position of each dot relative to each gate had not been determined. Here, we demonstrated the formation of series-triple quantum dots by attaching three fine gates on the nanowire through the same oxidation process. A 3×3-dimensional capacitance matrix among the three gates and the three dots were evaluated from the stability diagrams for electrons in the dots. The matrix makes it possible to assess the detailed positions of the triple quantum dots relative to the three fine gates. The result shows that each quantum dot was formed beneath a fine gate. The method not only makes the device compact but also self-aligns a gate electrode onto each quantum dot. Self-alignment is desirable when integrating multiple quantum dots with individual control gates.

II. DEVICE FABRICATION
Device fabrication is outlined in a sequence of diagrams [ Fig. 1(a)-1(d)]. The triple quantum dots were formed automatically in the Si nanowire under the three fine gates by the two thermal oxidation steps for the nanowire [ Fig. 2(a)]. The nanowire was formed by electron-beam lithography and dry etching of the 25-nm-thick Si top layer of a silicon-on-insulator (SOI) wafer with a buried oxide layer of 400-nm thickness [ Fig. 1(a)]. The wire width and length were 40 and 220 nm, respectively. Two tunnel barriers at the both ends of the nanowire were formed by PADOX at 1000 • C for 70 min in a dry oxygen atmosphere, and a single long quantum dot was automatically formed between the two wide Si two-dimensional (2D) layers corresponding to the source and drain electrodes [ Fig. 1(b)]. To suppress the oxidation of the 2D layers by PADOX, SiN cap layer was used. 38 A scanning electron microscope (SEM) image of the nanowire after the oxidation is shown in Fig. 1(e). Next, the three fine gate electrodes (G1, G2, and G3) made of 200-nm thick phosphorous-doped poly-silicon were attached to the nanowire using electron-beam lithography and dry etching. The width of the fine gate electrodes was 40 nm, and the gaps between the gate electrodes were 70 nm. The additional thermal oxidation of the nanowire was performed in a dry oxygen atmosphere at 700 • C for 270 min and at 1000 • C for 8 min. This oxidizes the Si nanowire more at the gap of the fine gate because the fine poly-silicon gates disturbed the nanowire beneath the gates from the oxidation. This made a constriction in the Si nanowire at the gap just between the fine gates. These constrictions act as tunnel barriers for splitting the quantum dots, and triple quantum dots (QD1, QD2, and QD3) were formed in the nanowire under the gate electrodes of G1, G2, and G3 [ Fig. 1(c)]. An SEM image of the nanowire after the formation of the three fine gate electrodes is shown in Fig. 1 dots is formed under each of the fine gates, the number of quantum dots can be increased by increasing the number of fine gates.

III. MEASUREMENT OF TRIPLE-QUANTUM DOT DEVICE AND THE METHOD FOR EVALUATION
The configuration of the triple quantum dots was investigated by measuring the charge stability diagrams following the application of three gate voltages (V 1 , V 2 , and V 3 ) to the each gate electrode (G1, G2, and G3). In order to open the channel of parasitic metal-oxide-semiconductor field-effect transistors formed in the 2D Si layers at both sides of the nanowire under the top gate, which act as the source and drain electrodes of the triple-quantum-dot device, the top gate and back gate (Si substrate) voltages of 0 V and 20 V were applied, respectively. 38 The temperature during measurements was about 8 K. The equivalent circuit of the triple quantum dots with three gate voltages is shown in Fig. 2(b). Gate capacitances between Gi (i = 1, 2, 3) and QD j ( j = 1, 2, 3) were defined as C ij . In this experiment, we evaluated all the gate capacitances of two sample devices, labeled Device-A and Device-B, by using the measured stability diagrams in the regime where the inter-dot coupling capacitances (C M1 and C M2 ) are much smaller than the total capacitance of each quantum dot. First, the stability diagrams of the double quantum dots as a function of two of the three gate voltages, V 1 and V 2 or V 2 and V 3 , were evaluated; this avoids the complexity inherent in the triple-quantum-dot stability diagram. In these diagrams, seven of the nine gate capacitances were obtained; C 13 and C 31 were not. To achieve the residual two capacitances as well as to confirm the accuracy of the seven capacitances, stability diagrams were drawn in the V 1 -V 3 plane with V 2 as a parameter.

IV. RESULTS AND DISCUSSION
We plotted the measured charge stability diagrams of Device-A (Fig. 3). Fig. 3(a) is a contour plot of the drain current (I D ) at the drain voltage V D of 5 mV as a function of V 1 and V 2 at constant V 3 . The current peaks form a characteristic checker-board pattern 21 associated with the stability diagram of the double quantum dot system. Although the current peak modulation in parallel along the direction of V 2 axis was appeared because of the coupling between G2 and QD3, the current peaks were observed when the QD1 and QD2 resonate. This is because the effect of the Coulomb oscillation for QD3 is small as the variation in V 2 is small and V 3 is fixed. In other words, the stability diagram was considered to be the characteristic of double quantum dots composed of QD1 and QD2 when the effect of QD3 was almost ignored. The yellow lines (dot-and-dash lines) and red lines (broken lines) connected the current peaks of a pair of triple-points ignoring anti-crossing characteristics and represent the boundaries of charge transitions in the double quantum dots. 12,13 The gradients of the yellow and red lines distinguish the boundaries of the charge transitions as belonging to QD1 and QD2, respectively. Four gate capacitances, C ij (i = 1, 2, j = 1, 2), can be evaluated from the two periods and gradients. Fig. 3(b) shows an enlargement of Fig. 3(a). The periods and gradients of the yellow lines were defined as P V1 and dV 1 /dV 2 [ Fig. 3(b)]. The gate capacitances between QD1 and the two gates, G1 and G2, are calculated from C 11 = e/P V1 (e is elementary charge) and C 21 = dV 1 /dV 2 × C 11 , yielding C 11 = 3.27 aF and C 21 = 2.29 aF. Similarly, the gate capacitances between QD2 and the two gates, G1 and G2, were calculated from the periods P V2 and gradients dV 2 /dV 1 of the red lines as C 22 = e/P V2 = 3.64 aF, and C 12 = dV 2 /dV 1 × C 22 = 0.23 aF. Here, these values were obtained by averaging the data evaluated from several lines, because the periods and gradients of the lines are not constant as the measured area falls within the few-electron regime although the dot has several tens of electrons. 37 From the stability diagram as a function of V 2 and V 3 [ Fig. 3(c)], the effect of QD1 is expected to be negligibly small in this measurement because of small variation of V 2 and fixed V 1 . Two lines of different gradients can be drawn by connecting the observed current peaks, suggesting a double quantum dots forms from QD2 and QD3. The gradients of the red and green lines distinguish the boundaries of the charge transitions in QD2 and QD3, respectively. Although the gradient of the red line is different from that in Fig. 3(a) as the capacitance ratio of C 22 /C 12 and C 22 /C 32 are different, the periods for the variation of V 2 are almost the same. The gate capacitances between the dots (QD2 and QD3) and the gates, G2 and G3, were calculated to be C 22 = 3.20 aF, C 23 = 1.10 aF, C 32 = 0.58 aF, and C 33 = 1.58 aF from the periods (P V2 and P V3 ) and gradients (dV 3 /dV 2 and dV 2 /dV 3 ) of the two lines. The slight difference in C 22 calculated from the two stability diagrams [ Fig. 3(a) and 3(c)] may be attributed to the fluctuation of the effective gate capacitance in the few-electron regime. 37 The averaged C 22 is 3.42. As the seven gate capacitances can be evaluated from the measurements from double quantum dots formed from QD1 and QD2 or QD2 and QD3, the other capacitances (C 13 and C 31 ) were not evaluated and believed to be much smaller than the other gate capacitances because the spatial separation from the dots is large. The result clearly shows that the gate capacitances C ii were always the largest among C i1 , C i2 , and C i3 , i.e, each gate Gk couples more strongly to QDk (k = 1, 2, 3). This fact indicates that each quantum dot was formed beneath a fine gate.
For further analysis, stability diagrams of triple quantum dots were plotted giving I D as a function of V 1 and V 3 at constant V 2 . Fig. 4   of these lines, which correspond to e/C ij , agree well with the ones achieved above from the stability diagrams [ Fig. 3(a) and 3(c)]. The stability diagram of the triple quantum dots therefore have been successfully measured (Fig. 4). The gate capacitances between the three dots, QD1, QD2, and QD3, and the two gates, G1 and G3, were calculated from the periods and gradients of each line, yielding C 11 = 3.20 aF, C 12 = 0.23 aF, C 13 = 0.06 aF, C 31 = 0.03 aF, C 32 = 0.57 aF, and C 33 = 1.23 aF. In Fig. 4(a)-4(c), the red lines shift to higher V 1 and V 3 with decreasing V 2 whereas the yellow and green lines remained nearly unchanged. This means that the coupling of G2 with QD2 was stronger than that with QD1 and QD3. The shifts in V 2 for each change ∆V 2 = 10 mV were found to be about 5 mV in V 1 axis for QD1 (∆V 1y , yellow lines), about 60 mV in V 3 axis for QD2 (∆V 3r , red lines), and about 10 mV in V 3 axis for QD3 (∆V 3g , green lines). Subscripts, y, r, and g, refer to the yellow, red, and green lines, respectively. The other gate capacitances can be calculated from the equations Note C 21 is also written as C 21 = ∆V 3y /∆V 2 × C 31 = dV 3 /dV 1 × ∆V 1y /∆V 2 × C 31 . The evaluated capacitances were C 21 = 1.60 aF, C 22 = 3.42 aF, and C 23 = 1.23 aF. These capacitances almost correspond with those calculated from the stability diagrams [ Fig. 3(a) and 3(c)]. All the gate capacitances of the Device-A are summarized in Table I  gate capacitances of each quantum dot are also listed in the column headed C g -total, where the gate capacitances of the top and back gates were ignored because these capacitances are believed to be much smaller than the total gate capacitances. An important result from Table I is always largest among C ik (k = 1, 2, 3). This means that three quantum dots were formed beneath their respective gates and are mainly controlled by them. From Table I, the distribution of capacitances are asymmetric and a little irregular. The variation of each capacitances also provides important information about dot sizes and dot positions relative to each fine gate. QD1 has the largest C g -total. The variation of C g -total might be attributed to the misalignment of the fine gates along the nanowire during electron-beam lithography. Fig. 5 schematically presents the positional relationship between the dots (dotted circles), the fine gates (dot-and-dash square with round corner), and the nanowire (broken line), as estimated from the gate capacitances listed in Table I. The fine gates are believed to be shifted toward the direction of the drain electrode, making the size of QD1 bigger and QD3 smaller (Fig. 5). In addition, the tunnel barrier formed between QD1 and QD2 is expected to be shifted toward the QD2 because, from the SEM image [ Fig. 1(e)], some narrow parts are present in the nanowire because of fluctuations occurring during lithography. Because the width of nanowire is mainly narrowed by the additional oxidation, the tunnel barrier will be preferentially formed close to the initial structural constriction of the nanowire. For precise control of the size and position of each quantum dot, improving the precision of the structure of the nanowire and the alignment of gates along the nanowire is needed. Achieving this can be done by the improvements in the lithography.
For Device-B, the characteristics of its double quantum dots were confirmed from the measured stability diagrams, Fig. 6(a) and 6(b), as a functions of V 1 and V 2 and of V 2 and V 3 , respectively. These results clearly shows the formation of the triple quantum dots. Similar to Fig. 3, the boundaries of the charge transition in each quantum dot were drawn by connecting the thermally diffused current peaks, and the gate capacitances were calculated from the periods and gradients of these lines. The stability diagrams as a function of V 1 and V 3 for various values V 2 were also measured and gate capacitances calculated (Table II). Although values of C ii for the Device-B also tend to be large, G3 couples more strongly to QD2 than to QD3. The result is also explained by the fluctuation of nanowire width and slight misalignment of the fine gates attached along the nanowire. From C g−total for each quantum dot of the two devices A and B, the size and position of triple quantum dots is found to be different between the devices despite the similarity in design. Differences in dot structure are also believed to occur from imprecisions during lithography.

V. CONCLUSION
Triple quantum dot serial devices with control gates attached were successfully fabricated with the PADOX of Si nanowire and an additional oxidation through the gaps between the gates. From the stability diagrams for each of the two devices drawn by using three gate voltages, the formation of triple quantum dots was confirmed and the gate capacitances among the three gates and three quantum dots were evaluated. By evaluating gate capacitances between gates and dots, each quantum dot was found to form almost under a gate. The method demonstrated here enables many quantum dots to be simply fabricated in series with individual control gates attached, providing a new way to integrated coupled Si nano-dots for future single-electron transfer devices and/or quantum-bit devices.
The gate capacitances for the two devices were different although the design of the devices was the same. The variation in capacitances is believed to be attributed to the fluctuation in the initial nanowire width and the misalignment of the gates attached to the nanowire caused by the electron-beam lithography. These problems can be solved with improvements in the lithography in the future.