A two-in-one process for reliable graphene transistors processed with photolithography

Research on graphene field-effect transistors (GFETs) has mainly relied on devices fabricated using electron-beam lithography for pattern generation, a method that has known problems with polymer contaminants. GFETs fabricated via photo-lithography suffer even worse from other chemical contaminations, which may lead to strong unintentional doping of the graphene. In this letter, we report on a scalable fabrication process for reliable GFETs based on ordinary photo-lithography by eliminating the aforementioned issues. The key to making this GFET processing compatible with silicon technology lies in a two-in-one process where a gate dielectric is deposited by means of atomic layer deposition. During this deposition step, contaminants, likely unintentionally introduced during the graphene transfer and patterning, are effectively removed. The resulting GFETs exhibit current-voltage characteristics representative to that of intrinsic non-doped graphene. Fundamental aspects pertaining to the surface engineering employed in this work are investigated in the light of chemical analysis in combination with electrical characterization.

A two-in-one process for reliable graphene transistors processed with photo-lithography Research on graphene field-effect transistors (GFETs) has mainly relied on devices fabricated using electron-beam lithography for pattern generation, a method that has known problems with polymer contaminants.GFETs fabricated via photo-lithography suffer even worse from other chemical contaminations, which may lead to strong unintentional doping of the graphene.In this letter, we report on a scalable fabrication process for reliable GFETs based on ordinary photo-lithography by eliminating the aforementioned issues.The key to making this GFET processing compatible with silicon technology lies in a two-in-one process where a gate dielectric is deposited by means of atomic layer deposition.During this deposition step, contaminants, likely unintentionally introduced during the graphene transfer and patterning, are effectively removed.The resulting GFETs exhibit current-voltage characteristics representative to that of intrinsic non-doped graphene.Fundamental aspects pertaining to the surface engineering employed in this work are investigated in the light of chemical analysis in combination with electrical characterization.V C 2015 Author(s).All article content, except where otherwise noted, is licensed under a Creative Commons Attribution 3.0 Unported License.[http://dx.doi.org/10.1063/1.4935985]3][4] The investigation of the transport properties of graphene and the fabrication of graphene field effect transistors (GFETs) requires micro-structuring for which electron-beam lithography (EBL) so far has been predominantly used. 1,5,6Since EBL is not compatible with mass production in electronics, a more efficient fabrication process relying on photo-lithography is desired.This could pave the way to integration of any devices based on such 2D materials with large-scale, standard silicon circuitry.][9] In general, the one-atom thickness makes graphene extremely vulnerable to, e.g., unwanted doping and hysteresis behavior resulting from chemical adsorbents, most notably the ambient water molecules and oxygen, 10,11 and trapped charges at the interfaces with the dielectrics. 3,12,13In addition, residues of Poly(methyl methacrylate) (PMMA), which is commonly used for graphene transfer and pattern generation by means of EBL, 14 and photoresist (PR) in photo-lithographic process 7,8 will also affect the graphene.The common photoresist has been shown to have more adverse effect on the properties of graphene than the PMMA has. 7,8Great effort has been made to prevent GFETs from being affected by the unintentional doping and hysteresis by means of thermal annealing, 8 the use of substrates with selfassembled monolayer (SAM), 13 and passivation of graphene for instance with parylene, 11 and atomic layer deposition (ALD) of, e.g., Al 2 O 3 . 9In another attempt, a sacrificial layer like Au has been employed as an interlayer to avoid the direct contact of graphene with photoresists. 15However, during subsequent wet etching steps used for pattern transfer from the photoresist graphene is exposed to unwanted chemicals.Unintentional doping can lead to degradation of the graphene quality, low yield, poor reproducibility, and instability.
In this work, we present a photo-lithography-based process for scalable fabrication of reliable dual gate (DG-) GFETs.A Au layer is used to prevent graphene from being in direct contact with photoresist and subsequently is patterned to form source and drain electrode.Most notable is the twoin-one process that creates a top gate (TG) dielectric and simultaneously effectively removes the contaminants, repeatedly yielding graphene devices of non-doping behavior.
The key steps in the process flow for fabricating the devices are summarized in Fig. 1(a).Single-layer graphene films (SLGs) were produced by means of thermal chemical vapor deposition (CVD) over a Cu foil at 1000 C. The grown SLGs were transferred onto oxidized highly doped n-type (n þþ ) silicon substrates using the conventional polymer-assist transfer technique with PMMA as a support (S1 in Fig. 1(a)).The Cu was etched off using FeCl 3 (aq) solution.The SLG was characterized by resonant Raman spectroscopy at 532 nm wavelength on a Renishaw "inVia" Raman Spectrometer.For GFET fabrication, a 100 nm Au layer was deposited by evaporation on the SLG/SiO 2 (S2 in Fig. 1(a)).This was followed by spin coating of PR and photo-lithography to define the device area.The Au and SLG outside the device area were removed by wet etching in KI 3 and reactive ion etching (RIE) with CHF 3 /O 2 , respectively (S3 in Fig. 1 conducted to define the channel area.Channels with different length and width were defined by etching the exposed Au in KI 3 , to form a back gate (BG-) GFET structure (S4 in Fig. 1(a)).The Al 2 O 3 TG dielectric was deposited by means of ALD using trimethylaluminum (TMA) and H 2 O as the source precursors (S5 in Fig. 1(a)).An Al seed-layer of 1 nm in nominal thickness was deposited by e-beam evaporation prior to the ALD process. 16Finally, a third photo-lithography step was used to make the Cu TG electrode, to form the DG-GFET structure (S6 in Fig. 1(a)).The TG electrode slightly overlaps the source and drain electrodes, ensuring full electrostatic control.Scanning electron microscopy (SEM) was used for morphological characterizations.X-ray photoelectron spectroscopy (XPS) was employed to detect the presence of impurities on graphene.To probe the Al 2 O 3 /graphene/SiO 2 interfaces, depth profiling XPS measurement was performed.It was conducted in such a way that signals of C, I, Fe, Al, and Si were monitored while the Al 2 O 3 was stepwise etched by sputtering.When the etching approaches and passes the interfaces of Al 2 O 3 /SLG/SiO 2 , the intensity of the Al signal decreases rapidly while that of C from the SLG appears and disappears.The moment of the highest intensity of the C peak, which coincides with the steepest Al slope, is when the interfaces of Al 2 O 3 /graphene/SiO 2 are reached.The GFETs were characterized electrically using a probe station with an Agilent 4155A parameter analyzer.
In Fig. 1(b), a Raman spectrum obtained by averaging over several spots on a fully grown graphene film (the right inset) is shown.The line shape of the 2D peak, the two times higher intensity of the 2D peak compared to the G peak, and the small D peak indicate that a single-layer graphene film with a low defect density exists over the whole sample area. 17The average grain size of the SLG is around 10 lm as shown on the left inset of Fig. 1(b) where the individual SLG flakes are visible on a graphene film, for which growth was stopped before the flakes merge.In the process steps from S2 to S4 in Fig. 1(a), the use of Au layer not only prevents the SLG film from being contaminated by photoresist but also forms source and drain electrode after being patterned.In order to grow high-quality Al 2 O 3 by ALD on the SLG film at 300 C, an ultrathin Al thin film is necessary as a seed layer 15 since the nucleation of Al 2 O 3 directly on graphene is difficult. 18As shown in the SEM image (Fig. 1(c)), the deposition of the thin Al film on the SLG results in a percolated Al film with dense narrow gaps.The subsequent ALD process with 300 cycles leads to a continuous Al 2 O 3 film of about 28 nm thickness.Following the process flow as illustrated in Fig. 1  when the BG voltage (V BG ) is swept between À10 and 10 V (solid curve in Fig. 2(a)).Possible impurities that can dope the SLG and cause the absence of a Dirac point include water and oxygen from the surroundings, 11 PMMA residues from the graphene transfer, 14,19 as well as impurities from the etchants, i.e., FeCl 3 and KI 3 solutions.The extrinsic doping is in this case so strong that the Dirac point is persistently unobservable even when the BG is extended to the range of À100 to 100 V (inset in Fig. 2(a)).Annealing the BG-GFET at 300 C for 2 h does not improve the transfer characteristics (the dashed-dotted curve in Fig. 2(a)).It has been reported that annealing at 180 C in air is sufficient to remove water and oxygen from graphene. 11The failure of dedoping the SLG by annealing alone indicates that adsorbents other than water and oxygen play an important role in our BG-GFETs.On the other hand, an ALD-Al 2 O 3 can act as an efficient passivation layer to block water and oxygen from the ambient. 9n this work, we also show that such ALD process effectively removes contamination and virtually dedopes the SLG.As shown in Fig. 2(b), an ALD-Al 2 O 3 grown at 300 C with an Al seed layer on the BG-GFETs (S5 in Fig. 1(a)) leads to the Dirac point close to 0 V when the BG voltage is swept between À10 V and 10 V and where the-drain-to-source voltage, V D , is 0.1 V.The non-doped behavior of SLG obtained here by the ALD process is highly reproducible, as is demonstrated by processing of several samples yielding the same results.The presence of the hysteresis is probably due to the interface and oxide traps existing in the SiO 2 or the Al 2 O 3 close to the SLG.Using a simple capacitance model, i.e., C BG ¼ 2.9 Â 10 À8 F/cm 2 for the 120-nm SiO 2 , the number of trapped charges per cm 2 , N, is estimated to N ¼ C GB DV BG /(2e) ¼ 1.8 Â 10 11 /cm 2 where DV BG is the shift of the Dirac point and e is the charge of an electron. 12his trapped charge density at the interfaces is of the same order as the effective density of interface, and oxide traps ($10 9 -10 11 /cm 2 ) at Si/SiO 2 interface of a conventional Si field effect transistor. 20 order to show the strength of the ALD-Al 2 O 3 process at 300 C in dedoping SLG, BG-GFETs with the SLGs covered with ALD-Al 2 O 3 grown at 100 C and AlO x deposited by means of e-beam evaporation (e-AlO x ), respectively, were also studied.As shown in Fig. 3 for the drain current versus gate voltage (I D -V BG ) in the range À100 and 100 V, the Dirac voltage point appears at $47 V for ALD-Al 2 O 3 at 100 C.This indicates that the SLG is partially dedoped under this condition.For the e-AlO x , the Dirac point remains absent which indicates that a simple passivation is not sufficient for restoring the intrinsic property of graphene.
In order to evaluate the applicability of the ALD process at 300 C in fabricating reliable GFETs, DG-GFETs were fabricated following the process steps consecutively from S1 to S6 illustrated in Fig. 1(a), in this case using Si (n þþ ) capped with a 200-nm thick SiO 2 .In Figs.2(c

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transfer characteristics are well controlled by the electrical doping in both cases.In addition, the current at the Dirac point stays nearly unchanged when the gate voltage for electrical doping is varied.This is in contrast to other DG-GFETs where the TG electrode is of smaller width than the separation between source and drain, which results in a sensitivity of the minimum current. 16,21ssuming the series resistance associated with the source and drain is negligible which is easily satisfied for a large gate length of 100 lm, the field-effect mobility l FE in the linear region can be calculated according to 3 where L ch and W ch are the length and width of the channel, respectively, g m is the transconductance, C G is the gate capacitance per area, and V D is the drain voltage (i.e., 0.1 V).The l FE is calculated to be 70 and 122 cm 2 V À1 s À1 for the electron and hole transport, respectively, in the linear range of the I D -V BG with V TG ¼ 0 V.When instead sweeping the TG voltage, and keeping V BG ¼ 0 V, the l FE is $80 and 99 cm 2 V À1 s À1 for the electron and hole transport, respectively.It should be noted that the effective gate capacitance C G can be well estimated by the capacitance of SiO 2 since the top gate voltage is fixed, and not left floating. 22The quantum capacitance, C Q (>2 lFcm À2 ), 23 can also be neglected since it is one order of magnitude higher than the capacitance of the 28-nm top gate dielectric, i.e., 0.29 lFcm À2 .In literature, the values of field effect mobility are in the range of 10 3 -10 4 cm 2 V À1 s À1 for the GFETs extensively reported earlier. 1,3,8,11,12,16,21Their gate length is normally in the range of sub-micrometer to several micrometers which is smaller than the typical domain size of SLG of 10 lm as shown in the inset of Fig. 1(b).For the 100-lm gate length, the carriers have to transport over $20 domain boundaries which scatter severely the carriers 24 and leads to a substantial reduction of the field effect mobility, as is seen here.
To shed light on the mechanism behind the impact of the ALD-Al 2 O 3 process on the effective dedoping of SLG, XPS is employed to probe the interfaces of Al 2 O 3 /SLG/SiO 2 in the BG-GFETs before and after the ALD processing.In addition to PMMA residue, the use of Cu etchant (FeCl 3 ) and Au etchant (KI 3 ) for graphene transfer (S1 in Fig. 1(a)) and electrode patterning (S4 in Fig. 1(a)), respectively, could further introduce impurities to the SLGs.The XPS detects a trace of Fe and I on the BG-GFETs while the signals of K and Cl are unobservable within the detection limit of XPS.It has been reported that iodine is a strong p-type dopant for graphene. 20As shown by the curve denoted as "SLG" in Fig. 4, the presence of iodine on the SLGs is detected with the characteristic peaks at 619.3 eV (I (3d 5/2 )) and 630.9 eV (I (3d 3/2 )).The iodine is rather stable on graphene when being annealed at 300 C at 500 Pa in N 2 for 2 h (the curve denoted as "SLG, 300 C").This is consistent with the stability of iodine on carbon nanotubes when annealed under ambient condition. 25At a reduced pressure, iodine becomes unstable at elevated temperature. 26With a $1 nm Al seed layer deposited on KI 3 -treated SLG that is annealed at 300 C, the presence of iodine at the interface remains (the curve denoted as "Al/SLG, 300 C").It is known that aluminum will react with iodine and form the compound AlI 3 27 which leads to the observed shift of the two peaks of iodine.
Measured by means of depth profiling XPS as described earlier, the iodine at the interface of Al/SLG becomes unobservable within the detection limit.This is measured on samples with Al 2 O 3 deposited at 100 and 300 C with an Al seed layer (denoted as "Al 2 O 3 /Al/SLG, 100 C" and "Al 2 O 3 /Al/ SLG, 300 C," respectively), and at 300 C without an Al seed layer (denoted as "Al 2 O 3 /SLG, 300 C").
The impact of the ALD-Al 2 O 3 process on the presence of iodine can be understood by the chemical reaction of aluminum, iodine, and water.During the channel opening in step S4 in Fig. 1(a), I 2 from the KI 3 solution p-dope the SLG leading to a pronounced shift of the Dirac point of the SLG (Fig. 2(a)).When subjected to the ALD-Al 2 O 3 at 300 C, the Al on the SLG reacts with I 2 through 2Al þ 3I 2 !2AlI 3 . 27 SLG without an Al seed layer, an initial Al is formed by the dissociation of TMA.Under the chamber pressure of the ALD, the AlI 3 converts from solid state and undergoes sublimation at temperatures beyond $234 C, which is calculated according to the Clausius-Clapeyron equation. 28,29The electrical results shown in Fig. 3 indicate that iodine is present at the interfaces of Al 2 O 3 /SLG/SiO 2 for the ALD-Al 2 O 3 at 100 C, assuming that no dopant other than iodine is present.This awaits confirmation using a method with sensitivity higher than that of XPS.In summary, a reproducible fabrication process based on ordinary photo-lithography for reliable DG-GFETs is presented.A Au layer is used as an interlayer between SLG and photoresist during pattern generation.It also forms electrodes for source and drain used in the DG-GFET.A two-inone process is applied to realize gate dielectric by means of ALD at 300 C, which simultaneously removes the main dopant iodine from the SLG.Compared to the conventional approach where resist is applied directly on graphene followed by electrode formation, 1,3,[7][8][9]30 the process flow presented in this work repeatedly leads to the virtually nondoped behavior of graphene. Theresults pave the way for a scalable manufacturing of GFETs, which is also applicable

P
. Ahlberg, a) M. Hinnemo, a) M. Song, X. Gao, J. Olsson, S.-L.Zhang, and Z.-B.Zhang b) Solid State Electronics, Department of Engineering Sciences, The A ˚ngstr€ om Laboratory, Uppsala University, 75121 Uppsala, Sweden (Received 8 August 2015; accepted 5 November 2015; published online 16 November 2015) (a)).A second photo-lithography step was a) P. Ahlberg, and M. Hinnemo contributed equally to the work.b) (a), DG-GFETs can be reproducibly fabricated.In Fig. 1(d), a top view photo of the DG-GFET is shown.The transistor has a channel width of 500 lm and a length of 100 lm and will be used throughout this letter For a BG-GFET, i.e., S4 in Fig. 1(a) with the photoresist removed, Dirac point is absent in the transfer characteristics

FIG. 1 .
FIG. 1.(a) Schematic process flow for a DG-GFET with key steps from SLG transfer onto an oxidized Si (n þþ ) capped with SiO 2 of 120 or 200 nm in thickness (S1), passivation of the SLG with Au (S2), removal of the unwanted Au and SLG for device isolation (S3), formation of the SLG channel (S4), ALD of Al 2 O 3 as gate dielectric on the SLG channel (S5) to deposition of the top Cu gate electrode (S6); (b) resonant Raman spectrum of a fully-grown SLG film and SEM image of a "premature" SLG film whose growth was ceased leading to the visible single-crystalline flakes (left inset) and that of a fully-grown SLG which single-crystalline flakes merge together (right inset) with the size of the two insets of 50 lm; (c) SEM image of an Al seed layer with 1 nm in nominal thickness on an SLG and (d) optical photo of a DG-GFET with the width of 500 and length of 100 lm, respectively.
FIG. 2. (a)Transfer characteristics of a BG-GFET without any ALD-Al 2 O 3 on top of the SLG when the BG voltage is swept in the range of À10 to 10 V (solid) and of À100 to 100 V in a loop (inset) before annealing, i.e., asprepared and after annealing at 300 C for 2 h at 500 Pascal in N 2 (dashed-dotted line); (b) transfer characteristics of a BG-GFET with a ALD-Al 2 O 3 of 28 nm (300 cycles with TMA/H 2 O precursors); (c) transfer characteristics of a DG-GFET when the BG voltage is swept in a loop with the TG voltage at À1.0, 0, and 1.0 V, respectively, and (d) when the TG voltage is swept in a loop with the BG voltage at À10, 0, and 10 V, respectively.All the devices shown here have gate length 100 lm and width 500 lm.The drain voltage is fixed at 0.1 V.