Microwave noise characterization of graphene field effect transistors

Chalmers Publication Library (CPL) offers the possibility of retrieving research publications produced at Chalmers University of Technology. It covers all types of publications: articles, dissertations, licentiate theses, masters theses, conference papers, reports etc. Since 2006 it is the official tool for Chalmers official publication statistics. To ensure that Chalmers research results are disseminated as widely as possible, an Open Access Policy has been adopted. The CPL service is administrated and maintained by Chalmers Library.

Microwave noise characterization of graphene field effect transistors M. Tanzid, a) M. A. Andersson, a) J. Sun, and J. Stake The microwave noise parameters of graphene field effect transistors (GFETs) fabricated using chemical vapor deposition graphene with 1 lm gate length in the 2 to 8 GHz range are reported.The obtained minimum noise temperature (T min ) is 210 to 610 K for the extrinsic device and 100 to 500 K for the intrinsic GFET after de-embedding the parasitic noise contribution.The GFET noise properties are discussed in relation to FET noise models and the channel carrier transport.Comparison shows that GFETs can reach similar noise levels as contemporary Si CMOS technology provided a successful gate length scaling is performed.V C 2014 Author(s).All article content, except where otherwise noted, is licensed under a Creative Commons Attribution 3.0 Unported License.[http://dx.doi.org/10.1063/1.4861115]Graphene 1 is promising as a channel material in high frequency and low noise field effect transistors (FETs).This is a consequence of the unique conical dispersion, 2 with superior mobility ð10 5 cm 2 =V sÞ for both type of carriers and intrinsic saturation velocity approaching the Fermi velocity (10 8 cm/s). 3ince the realization of the first top-gated 4 graphene field effect transistor (GFET) considerable effort has been exerted to push it towards higher frequencies.Nevertheless, issues such as mobility degradation caused by the gate dielectric and underlying substrate 5 or high metal to graphene contact resistance 6 still remain.Hence, only after de-embedding, the highest intrinsic f max and f T values reported till date for a GFET are 70 GHz (Ref.7) and 427 GHz, 8 respectively.
In addition to enhancing operating frequencies for envisioned future graphene electronics, it is important to understand the various noise processes in graphene devices.In certain applications, such as direct detectors, graphene benefits directly from its low levels of low frequency 1/f noise. 9n the other hand, when GFETs operate at microwave frequencies in amplifiers, 1/f noise is less important and thermally generated noise dominates.In this regime, the performance is quantified by the minimum noise temperature (T min ), for high frequency operation a figure-of-merit equally important to f T and f max .Thus, T min requires to be determined with highest possible accuracy, preferably from device level noise measurements, which provide all four transistor noise parameters. 10Importantly for device optimization, this enables accurate modeling which separates the thermal noise contributions within the device, intrinsic and extrinsic, contributing to T min .Moreover, it allows the de-embedding of measured noise temperature using correlation matrices. 11To date, only noise characterization of an amplifier 12 and a resistive subharmonic mixer 13 utilizing GFETs have been reported.The T min of 1 lm GFET made from exfoliated graphene 12 was predicted 10 to be $330 K and $75 K at 1 GHz for the extrinsic and intrinsic devices, respectively.
In this paper, results obtained from noise parameter measurements of GFETs using graphene grown by chemical vapor deposition (CVD) are presented.Additionally, noise models of the GFET gate and drain noise, excluding 10 and including 14 correlation, are validated and the results are related to channel carrier transport.
Graphene in this work was grown on copper foil in a cold-wall low-pressure CVD system (Black Magic, AIXTRON Nanoinstruments Ltd.) with CH 4 as precursor gas according to an established recipe. 15After the deposition, graphene was transferred onto a SiO 2 (300 nm)/Si substrate following a bubbling transfer procedure. 16The schematic diagram of GFET fabrication steps is shown in Fig. 1.Starting with graphene on the intended substrate (Fig. 1(a)), the GFET patterning was performed using electron beam (e-beam) lithography in four steps.In the first step, source/ drain contacts were patterned, 1 nm Ti/15 nm Pd/100 nm Au was evaporated by electron beam and lifted off (Fig. 1(b)).Subsequently, two 1 nm thick Al layers were deposited and oxidized on a hotplate at 170 C for 5 min (Fig. 1(c)).Mesas were patterned in the next e-beam step.Oxide and graphene were etched around the mesas by HCl and O 2 plasma, respectively (Fig. 1(d)), so that graphene remained only in the active device region.This alignment is crucial to minimize gate leakage current (I G ) and also for drain-source current (I DS ) to flow only through the channel and in turn increase transconductance (g m ).The 1 nm Al evaporation and oxidation step was repeated five times for a total thickness of $10 nm for the Al 2 O 3 gate oxide.In the subsequent e-beam step, gate fingers were patterned and 10 nm Ti/300 nm Au was evaporated and lifted off (Fig. 1(e)).In the last e-beam step, larger source/drain/gate pads for probing were patterned and oxide was etched from the overlap area of the smaller contacts using HCl.Finally, 10 nm Ti/305 nm Au was evaporated and lifted off (Fig. 1(f)).The gate length was L ¼ 1 lm and the device width was W ¼ 2 Â 30 lm.A relatively long channel length was chosen to achieve efficient gate modulation.The access length between gate fingers and source/drain contact was L a ¼ 100 nm.The SEM image of a final device is shown in Fig. 1(g).The small signal equivalent circuit of the device is shown in Fig. 2, which is similar to a standard FET equivalent circuit.The gate and drain pad resistances, R pg and R pd , arise from the insufficiently insulating substrate.The intrinsic part of the device is marked by a dashed rectangle in Fig. 2.
The measurements were performed in the 2-8 GHz range using an automated ATN electronic tuner system.The S-and noise parameters were measured at room temperature with an Anritsu 3797C vector network analyzer (VNA) and an Agilent N8975A noise figure analyzer (NFA), respectively, using a multiple impedance configuration.An optimum gate voltage, V GS ¼ 0.08 V, yielding the highest possible g m at a drain bias of V DS ¼ À1.5 V and I DS ¼ 22 mA was used.The high drain bias results in a difference between the gate source and gate drain voltages, as opposed to a back gate configuration.Still, the bias point is sufficient to the negative side of the minimum conductivity point to result in a majority of hole carriers, unipolar conduction, throughout the GFET channel. 17he bias is essential to obtain a high enough gain, reducing the uncertainty in the noise measurement.Operating at comparatively lower or higher drain bias either increased the uncertainty or degraded the GFETs by exerting electrical stress.The gate leakage current was I G % 100 pA, which is beneficial for a minimum level of shot noise ði 2 gs ¼ 2qI G Df Þ and thus negligible contribution at the measured noise level.
The extrinsic f T (from short circuit current gain jh 21 j ¼ 1) and f max (Mason's unilateral gain U ¼ 1) of the GFETs calculated from as-measured S-parameters were on the order of 10.5 GHz and 13 GHz, respectively.The measured and modeled S-parameters of a representative GFET are shown in Fig. 3.
The high frequency noise of a two-port network, such as a FET, is expressed through the noise temperature, T n .It depends on the source reflection coefficient, C s , presented to the device input according to where Z 0 is the reference impedance and T 0 ¼ 290 K.The noise parameters defined in Eq. ( 1) are the minimum noise temperature (T min ), optimum source reflection coefficient ðC opt Þ, where T n ¼ T min is attained, and the noise resistance (R n ) quantifying the sensitivity to increased noise temperature with C s 6 ¼ C opt .The measured noise parameters, as well as the calculated intrinsic device counterparts after de-embedding device parasitics, are shown in Figs.4-6, respectively.
The extracted values of the parasitic components of the GFET and the corresponding intrinsic device parameters are listed in Table I.The source and drain contact resistances are expressed as W is the resistance coming from the access region unaffected by the top gate and R mÀg ¼ q c =W is the metal to graphene contact resistance.R s and R d are considered to be equal due to the symmetric device layout.To obtain R s and R d , the sheet resistance of graphene, R sheet ¼ 583 X=ٗ, and contact resistivity, q c ¼ 76 Xlm, were extracted via transfer length method (TLM) measurements. 18Although R sheet is considerably higher than the values of highly doped III-V cap layers in HEMTs, the final value R s ¼ R d ¼ 135 Xlm is comparable to state-of-the-art HEMT technology.The gate resistance was obtained to be 54 X=mm from DC end-to-end measurement, i.e., measuring the DC resistance of the gate metalization stack and accounting for the small-signal operation FIG. 2. GFET small signal circuit with noise current definitions.In the PRC model, FIG. 3. Measured and modeled S-parameters of the GFET.
FIG. 4. Measured and modeled minimum noise temperature of the extrinsic and de-embedded GFET.
according to R g,RF ¼ R g,DC /3.The remaining parasitic components of the GFET were extracted using separately fabricated open and short structures.From the extrinsic GFET, the parasitics were de-embedded to obtain the intrinsic device parameters using two-port parameter manipulations. 19ubsequently, the intrinsic noise parameters were obtained by the noise correlation matrix approach. 11The noise current sources for the drain and induced gate noise are shown in Fig. 2. In the Pospieszalski model, 10 these are described by uncorrelated temperatures T d of R ds and T g of R i .On the other hand, P and R of the PRC model have an imaginary correlation factor jC. 14 The parasitics contribute thermal noise characterized by the ambient temperature, T a .Also shown in Figs.4-6 are the model fits with T d ¼ 1950 K and T g ¼ 700 K, corresponding to P ¼ 4, R ¼ 0.7, and C ¼ 0.4.Ideally in a FET, fluctuations in the drain current and gate voltage are perfectly correlated, C ! 1, which is closely fulfilled in HEMTs under low noise bias. 20The comparably low correlation in the GFET, despite the excellent aspect ratio ðt Al 2 O 3 =L g Þ, indicates degraded electrostatics possibly due to traps in the gate oxide.High quality gate stacks are thus essential to increase the cancellation of gate and drain noise 20 and improve the GFET microwave noise level.At the relatively high drain current used, the power dissipation creates an electron temperature above ambient. 21This is reflected in a gate temperature T g > T a .The measured noise parameters obey the relation 1 4G opt R n T 0 =T min < 2, where G opt ¼ Re½Y opt and Y opt is the source admittance when T n ¼ T min .Thus, the use of the noise models 10 is validated.The difference between extrinsic and intrinsic T min lies mainly in R pg , which is related to the insufficiently insulating Si substrate, rather than an inherent limitation of GFETs.A related issue is the modeled minimum extrinsic noise temperature (T min,ex ), which does not go through 0 K at zero frequency (Fig. 4).De-embedding of R pg results in minimum intrinsic noise temperature (T min,in ) identical 0 K at zero frequency for the GFET.In addition to T n , also the transistor gain is affected by the input impedance.For comparison, the source reflection coefficient for maximum stable gain (G MSG ) is also plotted in Fig. 5.It is apparent that the required C s for maximum gain is close to C opt for minimum noise.
To compare the noise performance of GFETs with other technologies, an appropriate frequency, f ¼ 2 GHz, is chosen considering the GFETs' f T and f max .For mature technologies, the device gate lengths are shorter and reported measurement frequencies in the literature are generally higher.Consequently, the normalized figure of merit T min /f/L (K/GHz/lm) is used to enable a more equitable comparison.The comparison of f T , T min , and T min /f/L of microwave FET technologies with GFETs at T a ¼ 300 K is presented in Table II.In the case of GFETs, T min ¼ T min,in is used in the comparison.For mature technologies, the intrinsic and extrinsic noise temperatures are similar and T min ¼ T min,ex is used.
For GFETs at 2 GHz, T min,ex ¼ 210 K and T min,in ¼ 100 K (from the model trend in Fig. 4) with G a ¼ 10.6 dB, i.e., the associated gain with the input matched for minimum noise, C s ¼ C opt .In comparison to the recent 45 nm Si CMOS technology node 22 using strained silicon and metal gates with corresponding reduction in T min , GFETs show similar performance in terms of noise judging from the T min /f/L values keeping in mind that the improvement in T min saturates at short gate lengths.This requires a successful scaling of the gate length with maintained performance for the GFET.Subtracting the pad noise, the GFET is not yet comparable to GaAs MESFETs 23 or III-V HEMT technologies. 24,25 limiting factor for the microwave noise is the reduced carrier mobility in GFETs, in this case the hole mobility l p ¼ 450 cm 2 /Vs.The mobility indicates device operation in  a linear regime, rather than velocity saturation, despite the high average field in the channel $1.4 V/lm. 17An upper limit estimate for the carrier velocity is set by the minimum carrier density, n 0 ¼ 2 Â 10 12 cm À2 , from thermal generation 2 and substrate impurities, 17 i.e., v < I DS =ðWqn 0 Þ $ 1 Â10 7 cm=s.This is in reasonable agreement with v sat ¼ 1 À 2 Â 10 7 cm=s at T a ¼ 300 K ambient with n ¼ 2-10 Â 10 12 cm À2 as limited by low energy SiO 2 phonons. 17This is in contrast to optimum low noise bias for III-V transistors, where V DS and V GS are set for velocity saturation and low I DS , respectively.An observed mobility increase at cryogenic temperatures in suspended graphene is likely to provide reduced noise temperature, due to the decay of scattering from acoustic phonons.Nevertheless, on SiO 2 substrate mobility is mainly limited by Coulomb scattering from charged impurities with little temperature dependence. 26Thus, also at cryogenic temperature, the noise performance will be limited by the substrate.Opposed to outer noise limiting mechanisms, inherently graphene has a low density of states close to the Dirac point. 2 This limits g m for a certain Fermi level shift, with disadvantageous effect on T min / 1=f T / 1=g m . 10pening of E g > 0 by a nanoribbon channel 2 could boost f T and thus T min further.
In summary, the device level noise characterization of a GFET at microwave frequencies is reported in this paper.The presented results are comparable with Si CMOS.A key step to improve the noise level is to enhance the channel mobility and reach saturated carrier transport.The substrate is then critical for v sat to be limited only by highly energetic phonons like in suspended graphene. 27Achieving gain for a wider range of biases enables a more complete study with enhanced measurement accuracy.

FIG. 5 .
FIG. 5. Measured and modeled optimum source reflection coefficient of the extrinsic and de-embedded GFET.
This work was supported by the Swedish Foundation of Strategic Research (SSF) and the Knut and Alice Wallenberg Foundation (KAW).TABLE II.Room temperature noise performance comparison of FETs.f is the frequency at which T min was measured.¼ T min,in.b T min ¼ T min,ex.

TABLE I .
Extracted parasitic and intrinsic parameters for the small-signal noise model in Fig.2with T a ¼ 297 K.