ABSTRACT
Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.
Flash memories based on organic field-effect transistors (OFETs) have been extensively studied because of their unique merits such as mechanical flexibility, low-cost manufacturing, light weight, and low-temperature processability.1–3 Among others, utilization of nano-floating-gate in OFET memories is superior because charge trapping into the nano-sized floating-gate, which is of key importance for memory performance, could be well controlled by varying density, size, and/or composition of the charge trapping nanostructures.4–6 Furthermore, the spatial discreteness of charge trapping sites is beneficial for scaling down of tunneling dielectric and improvement of retention capability.7,8 In a nano-floating-gate OFET memory, electron and hole trapping into the nano-floating-gate is the mechanism to open a memory window. The quantity of charge trapping is often indirectly derived from the threshold voltage (VT) shift (ΔVT) in device transfer characteristics, with positive and negative ΔVT corresponding to electron and hole trapping, respectively.4–6 Hence, it is highly needed to develop a direct and simple approach to probe charge trapping into the nano-floating-gate, which may offer insights for understanding the charge trapping mechanism and improving the memory performance.
Non-contact scanning probe microscopy (SPM), such as electrostatic force microscopy (EFM),9 dielectric force microscopy (DFM),10 and Kelvin probe force microscopy (KPFM),11,12 have been extensively applied to characterize local electronic properties of diverse nanomaterials.10–17 In a non-contact mode, the probe is lifted at a constant height above the surface of interest, where long-range forces are detected. Thus, the techniques avoid the direct surface contact, which enables in-depth investigations in a non-invasive way. In particular, KPFM is powerful to study surface work function,18–20 band bending and interfacial dipole,21–25 and also employed to quantitatively evaluate charge quantity trapped in insulators.26–30
In this report, KPFM is used to simulate programming/erasing process and directly profile charge trapping into the nano-floating-gate in a pentacene-based OFET nonvolatile memory. It is demonstrated that the integration of surface potential change (ΔΨ) after programming/erasing reflects the quantity of electron/hole trapping. The charge trapping capability turns out to be approximately proportional to the positive/negative gate bias (VGS) at programming/erasing, which is in good agreement with the corresponding device behavior. Thus, KPFM can be a useful tool to investigate the working mechanism of OFET nonvolatile memories.
The experimental setup is illustrated in Fig. 1. For memory fabrication, heavily doped Si (n++, Silicon Quest) with 100-nm-thick SiO2 on top acts as the bottom control-gate covered by the control dielectric. After routine cleaning of the substrate, Au nanoparticles (Au-NPs) as the nano-floating-gate were prepared by sputtering onto SiO2.7,31 The average NP size is about 10 nm. Then, an approximately 10-nm-thick layer of polystyrene (PS, Sigma-Aldrich, weight-average molecular weight MW = 2000 kg/mol) was deposited on the Au-NPs by spin coating, followed by annealing at 100 °C for 15 min to prepare the tunneling dielectric. 7,31 Subsequently, 40-nm-thick pentacene was deposited on PS in high vacuum (Kurt J. Lesker, working pressure < 10−6 mbar) to form a patterned organic active layer. As the final step, Cu top electrodes as the drain and source were deposited on pentacene with a shadow mask.32 The channel length (L) and channel width (W) of the device are 50 μm and 750 μm, respectively.
The electrical measurements were performed at room temperature using a semiconductor parameter analyzer (Keithley 4200) in high vacuum (Lake Shore, working pressure < 10−5 mbar). As for surface potential characterization, to conduct a reliable comparison, the KPFM measurements (Bruker, Icon) were directly carried out in air on the identical PS surface of the OFET memory (see Fig. 1). N2 gas was flowed in the measuring chamber to maintain a low humidity (∼20%), as humidity may influence surface charge diffusion.26,28 The KPFM instrument was operated in the Peak Force tapping mode,33 with scanner oscillation frequency f0 of 2 kHz and amplitude of 150 nm. This offers a precise force control between the probe and sample surface and allows non-destructive potential probing on soft materials such as organic thin films, preserving their surface morphology during scanning.
Upon simulating programming/erasing in the OFET memory, the KPFM tip was grounded and positioned to the center of scanning region at the Peak Force tapping setpoint, and sample bias (analogous to VGS in the device) was applied for a particular time period to induce charge trapping into the nano-floating-gate. When sample bias is 50 V, electrons can be injected into the Au-NPs from the tip via tunneling; and the same is applicable for holes with sample bias of −50 V. Figures 2(a)–2(c) show the KPFM images on the PS surface before charge injection (flat), after electron injection (convex), and after hole injection (concave), respectively. It is clear that ΔΨ is prominent after charge trapping, whereas its spatial profile is hemisphere-like rather than point-like, presumably due to the horizontal charge diffusion among neighboring Au-NPs. The effective circular area for measurable ΔΨ is about 10 μm2 (see Figs. 2(b) and 2(c)). Note that the PS surface morphology remains unchanged in the whole process, as demonstrated in the topographic images shown in Figs. 2(d)–2(f).

FIG. 2. KPFM images of identical PS surface (a) without charge trapping, and after (b) electron and (c) hole trapping into buried Au-NPs, where programming/erasing time is 60 s, and programming bias and erasing bias are 50 V and −50 V, respectively. Corresponding topographic images of the PS surface (d) without charge trapping, and after (e) electron and (f) hole trapping.
Figure 3(a) schematically shows a relation between ΔΨ and the surface density of trapped charges in the nano-floating-gate (QFG). Without a sample bias, QFG should be screened partly by the surface density of opposite charges in the control-gate (QCG) and partly by the induced charges in the grounded tip. When measuring surface potential, KPFM gets a nullified sample bias (Vnull) by which the electrostatic force between the tip and the sample surface is canceled.30 In this case, QFG is screened only by QCG, where QFG = −QCG. Figure 3(b) illustrates the energy diagram at the nullified state. There is no potential drop on the PS layer, and thus the potential drop on SiO2 can be regarded as ΔΨ, which is a result of charge trapping into the nano-floating-gate. Therefore, ΔΨ satisfies the following equation:
where Ci is the capacitance per unit area of the SiO2 layer. Considering ΔΨ in Figs. 2(b) and 2(c) is spatially non-uniform, a concept of potential volume (with dimension of Vm2) is introduced, which is the 2-dimensional integration of ΔΨ. According to Eq. (1), the product of potential volume and Ci is then the total charge quantity injected from the tip during programming/erasing. Therefore, the KPFM measurements shown in Figs. 2(b) and 2(c) could play a useful role in directly probing the charge trapping mechanism into the nano-floating-gate.
| (1) |

FIG. 3. (a) Schematic illustration showing KPFM measurement on tunneling dielectric (PS) surface, below which nano-floating-gate (Au-NPs) is charged with surface density of QFG. (b) Energy diagram for hole trapping into Au-NPs when surface potential is measured, where all sample bias drops on control dielectric (SiO2).
In the following, the above physical picture is verified by comparing the device behavior with the KPFM results. Figure 4(a) shows the round-scan transfer characteristics in variant VGS range of the OFET memory, where the drain bias (VDS) is −3 V. The FE mobility (μFE) for holes in the linear regime is about 0.6 cm2/V s. The device possesses excellent retention capability and programming/reading/ erasing/reading (P/R/E/R) endurance, as demonstrated in Fig. S1.38 With increasing the VGS range, both positive and negative ΔVT occur,34,35 and the ΔVT data after programming/erasing are shown in Fig. 4(b). Significantly, the magnitude of ΔVT is dependent on programming/erasing VGS, following an approximately linear relation above a threshold (VGS > 25 V for programming and VGS < −30 V for erasing). In an OFET nano-floating-gate memory, as long as Ci is much smaller than the capacitance per unit area of the PS layer, QFG can be described by ΔVT as below:
Thus, VGS-dependent ΔVT shown in Fig. 4(b) indicates that charge trapping into the Au-NPs is controlled by the gate field, and the electron injection into the Au-NPs appears to be relatively easier than the hole injection. A possible reason for the latter is that the hole injection barrier is higher compared with the electron injection barrier at the pentacene/PS interface.36
| (2) |
Figures 5(a) and 5(b) show the corresponding KPFM results after programming and erasing, respectively. No matter for electron injection (positive ΔΨ) or for hole injection (negative ΔΨ), the potential volume by integrating ΔΨ is raised with increasing programming/erasing VGS. The VGS dependence is almost linear above threshold (VGS > 25 V for programming and VGS < −30 V for erasing), and this trend is very similar to the device results shown in Fig. 4(b). It thus indicates that the charge trapping in the device is a field-controlled process.37 Furthermore, under the same programming/erasing conditions, the potential volume for electron injection is always larger as compared with that for hole injection. This is consistent with the device behavior as well, supporting the argument that it is relatively easy to inject electrons rather than holes into the Au-NPs. On the other hand, the potential volume is also raised as the programming/erasing time period is increased, which can be ascribed to the horizontal charge diffusion away from the injection center during programming/erasing. The good consistency between the device behavior and KPFM results indicates the validity and usefulness of the present potential volume method.
In conclusion, KPFM is demonstrated to be a powerful technique to probe the charge trapping mechanism in organic nano-floating-gate memories, and the surface potential change by KPFM is a direct and non-destructive measure of trapped electrons/holes into the nano-floating-gate. The KPFM results coincide with the device behavior, indicating that both electrons and holes can be trapped and stored in the Au-NPs. The charge trapping quantity is VGS-dependent and follows a nearly linear relation, and the electron trapping into the nano-floating-gate is easier compared with the hole trapping. The current approach can not only be utilized to understand the working mechanism of OFET nonvolatile memories but also have great potential for in situ measurements on charge trapping phenomena in organic semiconducting devices.
This work was supported by the National Natural Science Foundation of China (Grant No. 61274019), the National Basic Research Development Program of China (973 Program, Grant No. 2011CB808404), the Collaborative Innovation Center of Suzhou Nano Science & Technology, the Qing Lan Project of Jiangsu Province, and the Priority Academic Program Development of Jiangsu Higher Education Institutions (PAPD).
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