Full Published Online: 28 September 2007
AIP Conference Proceedings 931, 297 (2007); https://doi.org/10.1063/1.2799387
more...View Affiliations
  • aNational Institute of Standards and Technology (NIST), Gaithersburg, MD 20899
  • bDepartment of Materials Science and Engineering, University of Maryland, College Park, MD 20742
View Contributors
  • K.‐S. Chang
  • N. D. Bassim
  • P. K. Schenck
  • J. Suehle
  • I. Takeuchi
  • M. L. Green
As the CMOS gate stack continues to scale to smaller dimensions, new materials must be introduced into the stack to keep pace with design requirements. One way to measure the properties of new materials systems is through the use of high‐throughput experimentation, called combinatorial methodology. We describe two examples of combinatorial experimental design for CMOS. In the first, we will demonstrate library design and growth of Al‐Hf‐Y‐O films for high‐k applications. In the second, we will demonstrate Ni‐Ti‐Pt metal gate libraries for Si/Hf02/metal gate electrode applications.
  1. © 2007 American Institute of Physics.