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Published Online: 10 August 2009
Accepted: July 2009

Gate-bias stress in amorphous oxide semiconductors thin-film transistors

Appl. Phys. Lett. 95, 063502 (2009); https://doi.org/10.1063/1.3187532
M. E. Lopes1, H. L. Gomes1, a), M. C. R. Medeiros1, P. Barquinha2, L. Pereira2, E. Fortunato2, R. Martins2, and I. Ferreira2
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  • 1Centre of Electronic Optoelectronics and Telecommunications (CEOT), Universidade do Algarve, Campus de Gambelas, 8005-139 Faro, Portugal
  • 2Department of Materials Science/CENIMAT/I3N and CEMOP-UNINOVA, Faculty of Sciences and Technology, New University of Lisbon, Campus da Caparica, 2829-516 Caparica, Portugal

  • a)Electronic mail: .

Abstract
A quantitative study of the dynamics of threshold-voltage shifts with time in gallium-indium zinc oxide amorphous thin-film transistors is presented using standard analysis based on the stretched exponential relaxation. For devices using thermal silicon oxide as gate dielectric, the relaxation time is 3×105 s at room temperature with activation energy of 0.68 eV. These transistors approach the stability of the amorphous silicon transistors. The threshold voltage shift is faster after water vapor exposure suggesting that the origin of this instability is charge trapping at residual-water-related trap sites.
The authors wish to thank the Portuguese Foundation for Science and Technology for financial support of this work to the research units CEOT CENIMAT/I3N and to projs. PTDC/EEA-ELC/64975/2006 and PTDC/CTM/73943/2006.

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